Coverage Report

Created: 2017-11-12 13:27

/home/liu/buildslave/linux-x64-runtests/build/lib/nnc/cmd/blas/ccv_nnc_blas.c
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Source (jump to first uncovered line)
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#include <ccv.h>
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#include <nnc/ccv_nnc.h>
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#include <nnc/ccv_nnc_internal.h>
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static int _ccv_nnc_gemm_forw_bitmask(const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  if (
(input_bitmasks[0] & 7u) == ((1u << 0) | (1u << 1) | (1u << 2)) && 65
output_bitmasks[0] == 1u65
)
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    return 1;
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  return 0;
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}
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static int _ccv_nnc_gemm_back_bitmask(const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  // Output the propagated error, gradient w.r.t. w and bias.
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  if (
(input_bitmasks[0] & 7u) == ((1u << 0) | (1u << 1) | (1u << 2) | (0 << 3)) && 27
output_bitmasks[0] == ((1u << 0) | (1u << 1) | (1u << 2))13
)
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    return 1;
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  // Don't propagate error, only gradient w.r.t. w and bias.
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if (16
(input_bitmasks[0] & 7u) == ((1u << 0) | (1u << 1) | (0 << 2) | (0 << 3)) && 16
output_bitmasks[0] == ((0 << 0) | (1u << 1) | (1u << 2))6
)
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    return 1;
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  return 0;
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}
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static void _ccv_nnc_gemm_tensor_auto_forw(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* const inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* const outputs, const int output_size)
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{
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  assert(output_size == 1);
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  outputs[0].type = inputs[0].type;
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  outputs[0].format = inputs[0].format;
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  outputs[0].datatype = inputs[0].datatype;
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  outputs[0].dim[1] = inputs[0].dim[1]; // batch size.
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  outputs[0].dim[0] = inputs[1].dim[0]; // from the weight matrix.
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  assert(inputs[1].dim[0] == cmd.blas.count);
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  assert(inputs[1].dim[0] == inputs[2].dim[0]); // from the bias matrix.
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}
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REGISTER_COMMAND(CCV_NNC_GEMM_FORWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_gemm_cpu_ref.c, ccv_nnc_gemm_cpu_opt.c)
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{
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  registry->bitmask = _ccv_nnc_gemm_forw_bitmask;
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  registry->tensor_auto = _ccv_nnc_gemm_tensor_auto_forw;
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}
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REGISTER_COMMAND(CCV_NNC_GEMM_BACKWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_gemm_cpu_ref.c, ccv_nnc_gemm_cpu_opt.c)
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{
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  registry->bitmask = _ccv_nnc_gemm_back_bitmask;
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  registry->tensor_auto = ccv_nnc_hint_tensor_auto_backward_from_inputs;
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}
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static int _ccv_nnc_axpy_forw_bitmask(const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  if (
(input_bitmasks[0] & 3u) == ((1u << 0) | (1u << 1)) && 2
output_bitmasks[0] == 1u2
)
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    return 1;
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  // It is OK to not having y
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0
  
if (0
(input_bitmasks[0] & 3u) == ((1u << 0) | (0u << 1)) && 0
output_bitmasks[0] == 1u0
)
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    return 1;
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  return 0;
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0
}
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static int _ccv_nnc_axpy_back_bitmask(const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  // w.r.t. both x and y
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  if (
(input_bitmasks[0] & 1u) == 1u && 15
output_bitmasks[0] == ((1u << 0) | (1u << 1))11
)
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    return 1;
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  // w.r.t. x
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if (9
(input_bitmasks[0] & 1u) == 1u && 9
output_bitmasks[0] == ((1u << 0) | (0u << 1))5
)
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    return 1;
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  // w.r.t. y
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if (4
(input_bitmasks[0] & 1u) == 1u && 4
output_bitmasks[0] == ((0u << 0) | (1u << 1))0
)
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    return 1;
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  return 0;
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}
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REGISTER_COMMAND(CCV_NNC_AXPY_FORWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_axpy_cpu_ref.c)
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{
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  registry->flags = CCV_NNC_CMD_ATTR_INPLACE;
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  registry->bitmask = _ccv_nnc_axpy_forw_bitmask;
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  registry->tensor_auto = ccv_nnc_hint_tensor_auto_forward_from_inputs;
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}
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REGISTER_COMMAND(CCV_NNC_AXPY_BACKWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_axpy_cpu_ref.c)
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{
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  registry->bitmask = _ccv_nnc_axpy_back_bitmask;
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  registry->tensor_auto = ccv_nnc_hint_tensor_auto_backward_from_gradient;
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}