Coverage Report

Created: 2017-11-12 13:27

/home/liu/buildslave/linux-x64-runtests/build/test/int/nnc/cudnn.tests.c
Line
Count
Source (jump to first uncovered line)
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#include "case.h"
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#include "ccv_case.h"
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#include <ccv.h>
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#include <nnc/ccv_nnc.h>
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#include <nnc/ccv_nnc_easy.h>
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#include <3rdparty/dsfmt/dSFMT.h>
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8
TEST_SETUP()
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{
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  ccv_nnc_init();
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}
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9.66M
#define INPUT_DIM (3)
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14.3k
#define OUTPUT_DIM (96)
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19.2M
#define INPUT_SIZE (224)
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#define OUTPUT_SIZE (112)
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56.4k
#define KERNEL_SIZE (7)
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#define BATCH_SIZE (64)
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TEST_CASE("cudnn forward convolution")
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1
{
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1
  if (!ccv_nnc_cmd_ok(CCV_NNC_CONVOLUTION_FORWARD, CCV_NNC_BACKEND_GPU_CUDNN))
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0
    return;
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1
  
ccv_nnc_tensor_t* a = ccv_nnc_tensor_new(0, 1
CPU_TENSOR_NHWC1
(BATCH_SIZE, INPUT_SIZE, INPUT_SIZE, INPUT_DIM), 0);
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1
  ccv_nnc_tensor_t* b = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(BATCH_SIZE, OUTPUT_SIZE, OUTPUT_SIZE, OUTPUT_DIM), 0);
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1
  ccv_nnc_cmd_t cmd = CMD_CONVOLUTION_FORWARD(OUTPUT_DIM, KERNEL_SIZE, KERNEL_SIZE, INPUT_DIM);
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1
  cmd.backend = CCV_NNC_BACKEND_CPU_REF;
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  assert(cmd.backend >= 0);
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  ccv_nnc_hint_t hint = ccv_nnc_hint_auto(cmd.info, a->info, b->info);
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1
  assert(ccv_nnc_hint_verify(hint, cmd.info, a->info, b->info) == 0);
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1
  ccv_nnc_tensor_t* w = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(OUTPUT_DIM, KERNEL_SIZE, KERNEL_SIZE, INPUT_DIM), 0);
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1
  ccv_nnc_tensor_t* bias = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(OUTPUT_DIM), 0);
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1
  // configure the inlets.
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1
  dsfmt_t dsfmt;
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1
  dsfmt_init_gen_rand(&dsfmt, 0);
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1
  int i;
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14.1k
  for (i = 0; 
i < 14.1k
INPUT_DIM14.1k
*
KERNEL_SIZE14.1k
*
KERNEL_SIZE14.1k
*
OUTPUT_DIM14.1k
;
i++14.1k
)
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14.1k
    
w->data.f32[i] = dsfmt_genrand_open_close(&dsfmt) / (14.1k
INPUT_DIM14.1k
*
KERNEL_SIZE14.1k
*
KERNEL_SIZE14.1k
);
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9.63M
  for (i = 0; 
i < 9.63M
INPUT_SIZE9.63M
*
INPUT_SIZE9.63M
*
INPUT_DIM9.63M
*
ccv_max9.63M
(1, BATCH_SIZE);
i++9.63M
)
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9.63M
    a->data.f32[i] = dsfmt_genrand_open_close(&dsfmt);
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97
  for (i = 0; 
i < 97
OUTPUT_DIM97
;
i++96
)
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96
    
bias->data.f32[i] = (float)i / 96
OUTPUT_DIM96
;
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  // Copy generated matrix values over to GPU.
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  ccv_nnc_tensor_t* ga = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(00, BATCH_SIZE, INPUT_SIZE, INPUT_SIZE, INPUT_DIM), 0);
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1
  ccv_nnc_tensor_t* gw = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(00, OUTPUT_DIM, KERNEL_SIZE, KERNEL_SIZE, INPUT_DIM), 0);
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1
  ccv_nnc_tensor_t* gwo = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(00, OUTPUT_DIM, INPUT_DIM, KERNEL_SIZE, KERNEL_SIZE), 0);
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  ccv_nnc_tensor_t* gbias = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(00, OUTPUT_DIM), 0);
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  ccv_nnc_cmd_t move = ccv_nnc_cmd(CCV_NNC_DATA_TRANSFER_FORWARD, 0, ccv_nnc_cmd_auto, 0);
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  move.backend = CCV_NNC_BACKEND_GPU_REF;
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  assert(move.backend >= 0);
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1
  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, 
TENSOR_LIST1
(a, w, bias),
TENSOR_LIST1
(ga, gw, gbias), 0);
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1
  ccv_nnc_cmd_exec(cmd, hint, 0, 
TENSOR_LIST1
(a, w, bias),
TENSOR_LIST1
(b), 0);
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1
  ccv_nnc_tensor_t* gc = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(00, BATCH_SIZE, OUTPUT_SIZE, OUTPUT_SIZE, OUTPUT_DIM), 0);
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1
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1
  ccv_nnc_cmd_t transform = ccv_nnc_cmd(CCV_NNC_FORMAT_TRANSFORM_FORWARD, 0, ccv_nnc_cmd_auto, 0);
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  transform.backend = CCV_NNC_BACKEND_GPU_CUDNN;
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  assert(transform.backend >= 0);
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  ccv_nnc_stream_context_t* stream_context = ccv_nnc_stream_context_new(CCV_STREAM_CONTEXT_GPU);
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  ccv_nnc_cmd_exec(transform, ccv_nnc_no_hint, 0, 
TENSOR_LIST1
(gw),
TENSOR_LIST1
(gwo), stream_context);
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  ccv_nnc_stream_context_wait(stream_context);
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1
  ccv_nnc_tensor_free(gw);
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1
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  cmd.backend = CCV_NNC_BACKEND_GPU_CUDNN;
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  assert(cmd.backend >= 0);
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1
  cmd.algorithm = -1;
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1
  cmd = ccv_nnc_cmd_autotune(cmd, 1 * 1024 * 1024 * 1024, hint, 0, 
TENSOR_LIST1
(ga, gwo, gbias),
TENSOR_LIST1
(gc), stream_context);
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1
  assert(CCV_NNC_EXEC_SUCCESS == ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(ga, gwo, gbias), TENSOR_LIST(gc), stream_context));
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1
  ccv_nnc_stream_context_wait(stream_context);
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1
  ccv_nnc_stream_context_free(stream_context);
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1
  ccv_nnc_tensor_t* c = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(BATCH_SIZE, OUTPUT_SIZE, OUTPUT_SIZE, OUTPUT_DIM), 0);
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1
  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, 
TENSOR_LIST1
(gc),
TENSOR_LIST1
(c), 0);
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1
  
REQUIRE_ARRAY_EQ_WITH_TOLERANCE1
(float, b->data.f32, c->data.f32, OUTPUT_DIM * OUTPUT_SIZE * OUTPUT_SIZE, 1e-5, "output from cudnn should match from CPU")
;1
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1
  ccv_nnc_tensor_free(c);
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1
  ccv_nnc_tensor_free(gc);
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1
  ccv_nnc_tensor_free(bias);
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1
  ccv_nnc_tensor_free(w);
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1
  ccv_nnc_tensor_free(b);
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1
  ccv_nnc_tensor_free(a);
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1
  ccv_nnc_tensor_free(gbias);
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1
  ccv_nnc_tensor_free(gwo);
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1
  ccv_nnc_tensor_free(ga);
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1
}
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#include "case_main.h"