Coverage Report

Created: 2021-04-05 03:19

/home/liu/buildslave/linux-x64-runtests/build/lib/nnc/cmd/adam/ccv_nnc_adam_cpu_ref.c
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#include "ccv.h"
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#include "ccv_internal.h"
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#include "nnc/ccv_nnc.h"
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#include "nnc/ccv_nnc_easy.h"
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#include "nnc/ccv_nnc_internal.h"
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#ifdef USE_OPENMP
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#include <omp.h>
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#endif
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#ifdef USE_DISPATCH
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#include <dispatch/dispatch.h>
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#endif
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// Shared methods.
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#include "../_ccv_nnc_cpu_ref.h"
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static int _ccv_nnc_adam_forw(const ccv_nnc_cmd_t cmd, const ccv_nnc_hint_t hint, const int flags, ccv_nnc_tensor_t* const* const inputs, const int input_size, ccv_nnc_tensor_t* const* const outputs, const int output_size, ccv_nnc_stream_context_t* const stream_context)
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{
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  assert(input_size == 4);
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  assert(output_size == 3);
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  ccv_nnc_tensor_view_t* const g = (ccv_nnc_tensor_view_t*)inputs[0];
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  ccv_nnc_tensor_view_t* const a = (ccv_nnc_tensor_view_t*)inputs[1];
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  ccv_nnc_tensor_view_t* const m = (ccv_nnc_tensor_view_t*)inputs[2];
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  ccv_nnc_tensor_view_t* const v = (ccv_nnc_tensor_view_t*)inputs[3];
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  ccv_nnc_tensor_view_t* const b = (ccv_nnc_tensor_view_t*)outputs[0];
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  ccv_nnc_tensor_view_t* const n = (ccv_nnc_tensor_view_t*)outputs[1];
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  ccv_nnc_tensor_view_t* const u = (ccv_nnc_tensor_view_t*)outputs[2];
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  assert(ccv_nnc_tensor_nd(a->info.dim) <= CCV_NNC_MAX_DIM + 2);
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  assert(ccv_nnc_tensor_nd(b->info.dim) <= CCV_NNC_MAX_DIM + 2);
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  // Assuming this is float 32.
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  int adim[CCV_NNC_MAX_DIM_ALLOC];
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  ccv_nnc_tensor_view_get_dim(a, adim);
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  assert(ccv_nnc_tensor_view_check_dim(g, adim));
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  assert(ccv_nnc_tensor_view_check_dim(m, adim));
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  assert(ccv_nnc_tensor_view_check_dim(v, adim));
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  assert(ccv_nnc_tensor_view_check_dim(b, adim));
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  assert(ccv_nnc_tensor_view_check_dim(n, adim));
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  assert(ccv_nnc_tensor_view_check_dim(u, adim));
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  assert(CCV_NNC_MAX_DIM == 2); // Need to change this logic for CCV_NNC_MAX_DIM == other number.
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  int ginc[CCV_NNC_MAX_DIM_ALLOC];
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  int ainc[CCV_NNC_MAX_DIM_ALLOC];
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  int minc[CCV_NNC_MAX_DIM_ALLOC];
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  int vinc[CCV_NNC_MAX_DIM_ALLOC];
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  int binc[CCV_NNC_MAX_DIM_ALLOC];
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  int ninc[CCV_NNC_MAX_DIM_ALLOC];
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  int uinc[CCV_NNC_MAX_DIM_ALLOC];
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  ccv_nnc_tensor_view_get_inc(g, ginc);
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  ccv_nnc_tensor_view_get_inc(a, ainc);
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  ccv_nnc_tensor_view_get_inc(m, minc);
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  ccv_nnc_tensor_view_get_inc(v, vinc);
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  ccv_nnc_tensor_view_get_inc(b, binc);
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  ccv_nnc_tensor_view_get_inc(n, ninc);
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  ccv_nnc_tensor_view_get_inc(u, uinc);
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  const int step = cmd.info.adam.step;
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  const float rate = cmd.info.adam.rate;
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  const float beta1 = cmd.info.adam.beta1;
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  const float beta2 = cmd.info.adam.beta2;
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  const float decay = cmd.info.adam.decay;
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  const float epsilon = cmd.info.adam.epsilon;
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  assert(step >= 1);
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  const float rate_inv_bias_correction1 = rate / (1 - powf(beta1, step));
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  const float inv_bias_correction2 = 1. / (1 - powf(beta2, step));
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  int i[CCV_NNC_MAX_DIM + 1];
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  int x;
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  float* gp = g->data.f32;
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  float* ap = a->data.f32;
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  float* mp = m->data.f32;
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  float* vp = v->data.f32;
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  float* bp = b->data.f32;
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  float* np = n->data.f32;
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  float* up = u->data.f32;
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  for (i[0] = 0; i[0] < adim[0]; 
i[0]++1.00k
)
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  {
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    for (i[1] = 0; i[1] < adim[1]; 
i[1]++1.00k
)
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    {
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      for (i[2] = 0; i[2] < adim[2]; 
i[2]++2.00k
)
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      {
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        for (x = 0; x < adim[3]; 
x++4.03k
)
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        {
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          float grad = gp[x];
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          grad += decay * ap[x];
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          const float mom = np[x] = beta1 * mp[x] + (1 - beta1) * grad;
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          const float vel = up[x] = beta2 * vp[x] + (1 - beta2) * grad * grad;
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          bp[x] = ap[x] - (mom * rate_inv_bias_correction1) / (sqrtf(vel * inv_bias_correction2) + epsilon);
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        }
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        gp += ginc[3];
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        ap += ainc[3];
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        mp += minc[3];
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        vp += vinc[3];
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        bp += binc[3];
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        np += ninc[3];
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        up += uinc[3];
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      }
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      gp += (ginc[2] - adim[2]) * ginc[3];
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      ap += (ainc[2] - adim[2]) * ainc[3];
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      mp += (minc[2] - adim[2]) * minc[3];
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      vp += (vinc[2] - adim[2]) * vinc[3];
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      bp += (binc[2] - adim[2]) * binc[3];
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      np += (ninc[2] - adim[2]) * ninc[3];
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      up += (uinc[2] - adim[2]) * uinc[3];
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    }
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    gp += (ginc[1] - adim[1]) * ginc[2] * ginc[3];
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    ap += (ainc[1] - adim[1]) * ainc[2] * ainc[3];
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    mp += (minc[1] - adim[1]) * minc[2] * minc[3];
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    vp += (vinc[1] - adim[1]) * vinc[2] * vinc[3];
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    bp += (binc[1] - adim[1]) * binc[2] * binc[3];
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    np += (ninc[1] - adim[1]) * ninc[2] * ninc[3];
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    up += (uinc[1] - adim[1]) * uinc[2] * uinc[3];
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  }
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  return CCV_NNC_EXEC_SUCCESS;
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}
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static int _ccv_nnc_adam_back(const ccv_nnc_cmd_t cmd, const ccv_nnc_hint_t hint, const int flags, ccv_nnc_tensor_t* const* const inputs, const int input_size, ccv_nnc_tensor_t* const* const outputs, const int output_size, ccv_nnc_stream_context_t* const stream_context)
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{
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  return CCV_NNC_EXEC_INVALID;
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}
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REGISTER_COMMAND_BACKEND(CCV_NNC_ADAM_FORWARD, CCV_NNC_BACKEND_CPU_REF)(ccv_nnc_cmd_backend_registry_t* const registry)
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{
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  registry->tensor_formats = CCV_TENSOR_FORMAT_NHWC | CCV_TENSOR_FORMAT_NCHW | CCV_TENSOR_FORMAT_CHWN;
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  registry->tensor_datatypes = CCV_32F;
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  registry->tensor_memory = CCV_TENSOR_CPU_MEMORY;
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  registry->algorithms = 1;
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  registry->exec = _ccv_nnc_adam_forw;
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}
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REGISTER_COMMAND_BACKEND(CCV_NNC_ADAM_BACKWARD, CCV_NNC_BACKEND_CPU_REF)(ccv_nnc_cmd_backend_registry_t* const registry)
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{
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  registry->tensor_formats = CCV_TENSOR_FORMAT_NHWC | CCV_TENSOR_FORMAT_NCHW | CCV_TENSOR_FORMAT_CHWN;
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  registry->tensor_datatypes = CCV_32F;
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  registry->tensor_memory = CCV_TENSOR_CPU_MEMORY;
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  registry->algorithms = 1;
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  registry->exec = _ccv_nnc_adam_back;
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}