Coverage Report

Created: 2021-04-05 03:19

/home/liu/buildslave/linux-x64-runtests/build/lib/nnc/cmd/compression/ccv_nnc_compression.c
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#include "ccv.h"
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#include "nnc/ccv_nnc.h"
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#include "nnc/ccv_nnc_internal.h"
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static int _ccv_nnc_lssc_forw_bitmask(const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  int i, j;
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  int input_flag = 0;
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  int input_bitcount = 0;
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  for (i = 0; i < input_bitmask_size; i++)
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  {
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    for (j = 0; j < 64; j++)
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      if (input_bitmasks[i] & (uint64_t)1 << j)
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      {
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        if (input_flag)
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          return 0;
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      } else
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        break;
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    input_bitcount += j;
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    if (j < 64)
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      input_flag = 1;
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    // Always like 1111100000, no 1110010101
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    for (; j < 64; j++)
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      if (input_bitmasks[i] & (uint64_t)1 << j)
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        return 0;
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  }
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  int output_flag = 0;
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  int output_bitcount = 0;
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  for (i = 0; i < output_bitmask_size; i++)
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  {
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    for (j = 0; j < 64; j++)
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      if (output_bitmasks[i] & (uint64_t)1 << j)
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      {
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        if (output_flag)
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          return 0;
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      } else
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        break;
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    output_bitcount += j;
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    if (j < 64)
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      output_flag = 1;
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    for (; j < 64; j++)
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      if (output_bitmasks[i] & (uint64_t)1 << j)
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        return 0;
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  }
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  return output_bitcount == input_bitcount && input_size == output_size && input_size == input_bitcount;
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}
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static int _ccv_nnc_lssc_back_bitmask(const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  int i, j;
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  int input_flag = 0;
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  int input_bitcount = 0;
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  for (i = 0; i < input_bitmask_size; i++)
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  {
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    for (j = 0; j < 64; j++)
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      if (input_bitmasks[i] & (uint64_t)1 << j)
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      {
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        if (input_flag)
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          return 0;
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      } else
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        break;
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    input_bitcount += j;
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    if (j < 64)
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      input_flag = 1;
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    // Always like 1111100000, no 1110010101
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    for (; j < 64; j++)
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      if (input_bitmasks[i] & (uint64_t)1 << j)
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        return 0;
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  }
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  int output_flag = 0;
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  int output_bitcount = 0;
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  for (i = 0; i < output_bitmask_size; i++)
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  {
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    for (j = 0; j < 64; j++)
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      if (output_bitmasks[i] & (uint64_t)1 << j)
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      {
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        if (output_flag)
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          return 0;
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      } else
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        break;
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    output_bitcount += j;
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    if (j < 64)
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      output_flag = 1;
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    for (; j < 64; j++)
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      if (output_bitmasks[i] & (uint64_t)1 << j)
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        return 0;
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  }
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  return output_bitcount <= input_bitcount && output_bitcount == output_size;
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}
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static void _ccv_nnc_lssc_tensor_auto_forw(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* outputs, const int output_size)
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{
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  int i, j;
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  assert(output_size <= input_size);
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for (i = 0; 10
i < output_size;
i++10
)
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  {
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    assert(inputs[i].datatype == CCV_16F);
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    const int nd = ccv_nnc_tensor_nd(inputs[i].dim);
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    const int hw = ccv_nnc_tensor_hw(inputs[i], nd);
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    outputs[i] = inputs[i];
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    for (j = 0; j < CCV_NNC_MAX_DIM - 1; 
j++10
)
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      outputs[i].dim[j + hw] = (inputs[i].dim[j + hw] + 3) / 4;
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    outputs[i].dim[CCV_NNC_MAX_DIM - 1 + hw] = (inputs[i].dim[CCV_NNC_MAX_DIM - 1 + hw] + 3) / 4 * 4;
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  }
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}
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static void _ccv_nnc_lssc_tensor_auto_back(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* outputs, const int output_size)
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{
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  int i, j;
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  assert(output_size <= input_size);
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  for (i = 0; i < output_size; i++)
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  {
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    assert(inputs[i].datatype == CCV_16F);
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    const int nd = ccv_nnc_tensor_nd(inputs[i].dim);
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    const int hw = ccv_nnc_tensor_hw(inputs[i], nd);
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    outputs[i] = inputs[i];
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    for (j = 0; j < CCV_NNC_MAX_DIM - 1; j++)
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      outputs[i].dim[j + hw] = inputs[i].dim[j + hw] * 4;
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    assert(outputs[i].dim[CCV_NNC_MAX_DIM - 1 + hw] % 4 == 0);
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  }
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}
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REGISTER_COMMAND(CCV_NNC_COMPRESSION_LSSC_FORWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_lssc_cpu_ref.c, gpu/ccv_nnc_lssc_gpu_ref.cu)
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{
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  registry->bitmask = _ccv_nnc_lssc_forw_bitmask;
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  registry->tensor_auto = _ccv_nnc_lssc_tensor_auto_forw;
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}
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REGISTER_COMMAND(CCV_NNC_COMPRESSION_LSSC_BACKWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_lssc_cpu_ref.c, gpu/ccv_nnc_lssc_gpu_ref.cu)
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{
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  registry->bitmask = _ccv_nnc_lssc_back_bitmask;
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  registry->tensor_auto = _ccv_nnc_lssc_tensor_auto_back;
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}
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//@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_COMPRESSION_LSSC_FORWARD)
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#define CMD_COMPRESSION_LSSC_FORWARD() ccv_nnc_cmd(CCV_NNC_COMPRESSION_LSSC_FORWARD, 0, ccv_nnc_cmd_auto, 0)
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//@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_COMPRESSION_LSSC_BACKWARD)
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#define CMD_COMPRESSION_LSSC_BACKWARD() ccv_nnc_cmd(CCV_NNC_COMPRESSION_LSSC_BACKWARD, 0, ccv_nnc_cmd_auto, 0)