Coverage Report

Created: 2021-04-06 02:31

/home/liu/buildslave/linux-x64-runtests/build/lib/nnc/cmd/roi/ccv_nnc_roi_align.c
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#include "ccv.h"
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#include "nnc/ccv_nnc.h"
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#include "nnc/ccv_nnc_easy.h"
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#include "nnc/ccv_nnc_internal.h"
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static int _ccv_nnc_roi_align_forw_bitmask(const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  if ((input_bitmasks[0] & 3u) == 3u && output_bitmasks[0] == 1u)
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    return 1;
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  return 0;
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}
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static int _ccv_nnc_roi_align_back_bitmask(const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  // We don't need the original input since roi align does averaging.
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  // We do, however, need the coordinate.
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  if ((input_bitmasks[0] & 5u) == ((1u << 0) | (0u << 1) | (1u << 2)) && output_bitmasks[0] == 1u)
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    return 1;
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  return 0;
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}
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static void _ccv_nnc_roi_align_tensor_auto_forw(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* outputs, const int output_size)
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{
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  assert(output_size == 1);
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  outputs[0] = inputs[0];
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  const int hw = ccv_nnc_tensor_hw(outputs[0], ccv_nnc_tensor_nd(outputs[0].dim));
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  assert(hw >= 0);
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  outputs[0].dim[hw] = ccv_max(cmd.size.dim[0], 1);
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  outputs[0].dim[hw + 1] = ccv_max(cmd.size.dim[1], 1);
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}
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static void _ccv_nnc_roi_align_tensor_auto_back(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* outputs, const int output_size)
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{
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  assert(output_size == 1);
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  outputs[0] = inputs[1];
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}
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REGISTER_COMMAND(CCV_NNC_ROI_ALIGN_FORWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_roi_align_cpu_ref.c, gpu/ccv_nnc_roi_align_gpu_ref.cu)
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{
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  registry->bitmask = _ccv_nnc_roi_align_forw_bitmask;
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  registry->tensor_auto = _ccv_nnc_roi_align_tensor_auto_forw;
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}
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REGISTER_COMMAND(CCV_NNC_ROI_ALIGN_BACKWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_roi_align_cpu_ref.c, gpu/ccv_nnc_roi_align_gpu_ref.cu)
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{
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  registry->bitmask = _ccv_nnc_roi_align_back_bitmask;
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  registry->tensor_auto = _ccv_nnc_roi_align_tensor_auto_back;
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}
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//@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_ROI_ALIGN_FORWARD)
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#define CMD_ROI_ALIGN_FORWARD(rows, cols) ccv_nnc_cmd(CCV_NNC_ROI_ALIGN_FORWARD, 0, ((ccv_nnc_cmd_param_t){.size={.dim={rows, cols,1}}}), 0)
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//@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_ROI_ALIGN_BACKWARD)
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#define CMD_ROI_ALIGN_BACKWARD(rows, cols) ccv_nnc_cmd(CCV_NNC_ROI_ALIGN_BACKWARD, 0, ((ccv_nnc_cmd_param_t){.size={.dim={rows, cols,1}}}), 0)