Coverage Report

Created: 2021-04-06 03:49

/home/liu/buildslave/linux-x64-runtests/build/lib/nnc/cmd/norm/ccv_nnc_norm.c
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#include "ccv.h"
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#include "nnc/ccv_nnc.h"
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#include "nnc/ccv_nnc_internal.h"
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static int _ccv_nnc_batch_norm_forw_bitmask(const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  // 5 inputs (x, scale, bias, mean, var)
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  // 1 outputs (y)
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  if (input_bitmasks[0] == 31u && 
output_bitmasks[0] == 1u675
)
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    return 1;
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  // 5 inputs (x, scale, bias, mean, var)
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  // 5 outputs (y, mean, var, saved_mean, saved_inv_var)
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  // Both mean and var in output is inplace for the input mean, var
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  if (input_bitmasks[0] == 31u && 
output_bitmasks[0] == 31u675
)
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    return 1;
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  return 0;
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}
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static int _ccv_nnc_batch_norm_enforce_inplace(const int input_idx, const int input_size, const int output_idx, const int output_size)
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{
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  if (input_idx == 3 && 
output_idx == 1455
)
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    return 1;
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  if (input_idx == 4 && 
output_idx == 2454
)
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    return 1;
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  return 0;
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}
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static int _ccv_nnc_batch_norm_back_bitmask(const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  // 0b110000001100001
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  // Inputs (gradient, 0, 0, 0, 0, x, scale, 0, 0, 0, 0, 0, 0, saved_mean, saved_inv_var)
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  // Output the propagated error, dscale and dbias
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  if ((input_bitmasks[0] & 24673u) == 24673u && 
(output_bitmasks[0] & 7u) == 7u377
)
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    return 1;
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  return 0;
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}
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static void _ccv_nnc_batch_norm_tensor_auto_forw(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* const inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* const outputs, const int output_size)
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{
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  assert(input_size == 5);
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  assert(output_size == 1 || output_size == 5);
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  outputs[0] = inputs[0];
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  if (output_size == 1)
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    return;
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  int i, j;
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  for (i = 1; i < output_size; 
i++7.62k
)
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  {
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    outputs[i] = inputs[0];
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    for (j = 0; j < cmd.bnorm.count; 
j++22.8k
)
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      outputs[i].dim[cmd.bnorm.axis[j]] = 1; // Reduce the dimension to 1.
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  }
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}
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static void _ccv_nnc_batch_norm_tensor_auto_back(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* const inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* const outputs, const int output_size)
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{
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  assert(input_size == 15);
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  assert(output_size == 5);
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  outputs[0] = inputs[0];
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  int i, j;
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  for (i = 1; i < output_size; 
i++6.64k
)
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  {
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    outputs[i] = inputs[0];
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    for (j = 0; j < cmd.bnorm.count; 
j++19.9k
)
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      outputs[i].dim[cmd.bnorm.axis[j]] = 1; // Reduce the dimension to 1.
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  }
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}
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REGISTER_COMMAND(CCV_NNC_BATCH_NORM_FORWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_batch_norm_cpu_ref.c, gpu/ccv_nnc_batch_norm_gpu_cudnn.cu)
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{
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  registry->bitmask = _ccv_nnc_batch_norm_forw_bitmask;
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  registry->tensor_auto = _ccv_nnc_batch_norm_tensor_auto_forw;
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  registry->enforce_inplace = _ccv_nnc_batch_norm_enforce_inplace;
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}
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REGISTER_COMMAND(CCV_NNC_BATCH_NORM_BACKWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_batch_norm_cpu_ref.c, gpu/ccv_nnc_batch_norm_gpu_cudnn.cu)
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{
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  registry->bitmask = _ccv_nnc_batch_norm_back_bitmask;
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  registry->tensor_auto = _ccv_nnc_batch_norm_tensor_auto_back;
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}
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//@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_BATCH_NORM_FORWARD)
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#define CMD_BATCH_NORM_FORWARD(_epsilon, _is_test, _momentum, ...) ccv_nnc_cmd(CCV_NNC_BATCH_NORM_FORWARD, 0, ((ccv_nnc_cmd_param_t){.size={.dim={1,1,1}},.bnorm={.epsilon=_epsilon,.is_test=_is_test,.momentum=_momentum,.count=LIST_COUNT(__VA_ARGS__),.axis={__VA_ARGS__}}}), 0)
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//@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_BATCH_NORM_BACKWARD)
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#define CMD_BATCH_NORM_BACKWARD(_epsilon, _is_test, _momentum, ...) ccv_nnc_cmd(CCV_NNC_BATCH_NORM_BACKWARD, 0, ((ccv_nnc_cmd_param_t){.size={.dim={1,1,1}},.bnorm={.epsilon=_epsilon,.is_test=_is_test,.momentum=_momentum,.count=LIST_COUNT(__VA_ARGS__),.axis={__VA_ARGS__}}}), 0)
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static int _ccv_nnc_layer_norm_forw_bitmask(const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  // 3 inputs (x, gamma, beta)
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  // 3 outputs (y, saved_mean, saved_inv_std)
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  if (input_bitmasks[0] == 7u && 
output_bitmasks[0] == 7u60
)
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    return 1;
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  // 3 inputs (x, gamma, beta)
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  // 1 output (y)
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  if (input_bitmasks[0] == 7u && 
output_bitmasks[0] == 1u24
)
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    return 1;
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  return 0;
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}
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static int _ccv_nnc_layer_norm_back_bitmask(const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  // 0b110011001
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  // Inputs (gradient, 0, 0, x, gamma, 0, 0, saved_mean, saved_inv_std)
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  // Output the propagated error, dgamma and dbeta
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  if ((input_bitmasks[0] & 409u) == 409u && 
(output_bitmasks[0] & 7u) == 7u75
)
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    return 1;
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  return 0;
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}
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static void _ccv_nnc_layer_norm_tensor_auto_forw(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* const inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* const outputs, const int output_size)
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{
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  assert(input_size == 3);
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  assert(output_size == 1 || output_size == 3);
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  outputs[0] = inputs[0];
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  if (output_size == 1)
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    return;
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  int i, j;
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  for (i = 1; i < output_size; 
i++874
)
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  {
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    outputs[i] = inputs[0];
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    for (j = 0; j < cmd.lnorm.count; 
j++910
)
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      outputs[i].dim[cmd.lnorm.axis[j]] = 1; // Reduce the dimension to 1.
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  }
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}
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static void _ccv_nnc_layer_norm_tensor_auto_back(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* const inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* const outputs, const int output_size)
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{
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  assert(input_size == 9);
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  assert(output_size == 1 || output_size == 3);
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  outputs[0] = inputs[0];
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  int i, j;
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  for (i = 1; i < output_size; 
i++670
)
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  {
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    outputs[i] = inputs[0];
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    for (j = 0; j < cmd.lnorm.count; 
j++682
)
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      outputs[i].dim[cmd.lnorm.axis[j]] = 1; // Reduce the dimension to 1.
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  }
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}
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REGISTER_COMMAND(CCV_NNC_LAYER_NORM_FORWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_layer_norm_cpu_ref.c, gpu/ccv_nnc_layer_norm_gpu_cudnn.cu)
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{
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  registry->bitmask = _ccv_nnc_layer_norm_forw_bitmask;
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  registry->tensor_auto = _ccv_nnc_layer_norm_tensor_auto_forw;
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}
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REGISTER_COMMAND(CCV_NNC_LAYER_NORM_BACKWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_layer_norm_cpu_ref.c, gpu/ccv_nnc_layer_norm_gpu_cudnn.cu)
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{
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  registry->bitmask = _ccv_nnc_layer_norm_back_bitmask;
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  registry->tensor_auto = _ccv_nnc_layer_norm_tensor_auto_back;
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}
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//@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_LAYER_NORM_FORWARD)
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#define CMD_LAYER_NORM_FORWARD(_epsilon, ...) ccv_nnc_cmd(CCV_NNC_LAYER_NORM_FORWARD, 0, ((ccv_nnc_cmd_param_t){.size={.dim={1,1,1}},.lnorm={.epsilon=_epsilon,.count=LIST_COUNT(__VA_ARGS__),.axis={__VA_ARGS__}}}), 0)
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//@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_LAYER_NORM_BACKWARD)
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#define CMD_LAYER_NORM_BACKWARD(_epsilon, ...) ccv_nnc_cmd(CCV_NNC_LAYER_NORM_BACKWARD, 0, ((ccv_nnc_cmd_param_t){.size={.dim={1,1,1}},.lnorm={.epsilon=_epsilon,.count=LIST_COUNT(__VA_ARGS__),.axis={__VA_ARGS__}}}), 0)