Coverage Report

Created: 2021-04-06 03:49

/home/liu/buildslave/linux-x64-runtests/build/test/int/nnc/compression.tests.c
Line
Count
Source
1
#include "case.h"
2
#include "ccv_case.h"
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#include "ccv_nnc_case.h"
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#include <ccv.h>
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#include <nnc/ccv_nnc.h>
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#include <nnc/ccv_nnc_easy.h>
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#include "3rdparty/dsfmt/dSFMT.h"
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TEST_SETUP()
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{
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  ccv_nnc_init();
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}
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static void prepare_nchw(const int N, const int C, const int H, const int W, ccv_nnc_tensor_t** const c_ptr, ccv_nnc_tensor_t** const cgc_ptr)
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4
{
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4
  ccv_nnc_tensor_t* const a = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, N, C, H, W), 0);
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4
  ccv_nnc_tensor_param_t a_params = CPU_TENSOR_NCHW(16F, N, C, H, W);
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4
  ccv_nnc_tensor_t* const a16 = ccv_nnc_tensor_new(0, a_params, 0);
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4
  ccv_nnc_tensor_param_t b_params;
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4
  ccv_nnc_hint_tensor_auto(CMD_COMPRESSION_LSSC_FORWARD(), &a_params, 1, ccv_nnc_no_hint, &b_params, 1);
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4
  ccv_nnc_tensor_t* const b16 = ccv_nnc_tensor_new(0, b_params, 0);
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4
  ccv_nnc_tensor_t* const c16 = ccv_nnc_tensor_new(0, a_params, 0);
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4
  ccv_nnc_tensor_t* const c = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, N, C, H, W), 0);
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4
  dsfmt_t dsfmt;
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4
  int i;
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4
  dsfmt_init_gen_rand(&dsfmt, 1);
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147M
  for (i = 0; i < N * C * H * W; 
i++147M
)
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147M
    a->data.f32[i] = dsfmt_genrand_open_close(&dsfmt) * 2 - 1;
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4
  ccv_float_to_half_precision(a->data.f32, (uint16_t*)a16->data.f16, N * C * H * W);
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4
  ccv_half_precision_to_float((uint16_t*)a16->data.f16, a->data.f32, N * C * H * W);
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4
  int x, y, ix, iy;
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172k
  for (i = 0; i < N * C; 
i++172k
)
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1.03M
    
for (y = 0; 172k
y < H;
y += 4860k
)
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10.6M
      
for (x = 0; 860k
x < W;
x += 49.80M
)
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9.80M
      {
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9.80M
        float* const ap = a->data.f32 + x + y * W + i * H * W;
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9.80M
        float v[4] = { ap[0], ap[1], ap[0] * 2 / 3 + ap[1] / 3, ap[0] / 3 + ap[1] * 2 / 3 };
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47.6M
        for (iy = 0; iy < ccv_min(y + 4, H) - y; 
iy++37.8M
)
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185M
          
for (ix = 0; 37.8M
ix < ccv_min(x + 4, W) - x;
ix++147M
)
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147M
            ap[iy * W + ix] = v[dsfmt_genrand_uint32(&dsfmt) % 4];
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9.80M
        ap[0] = v[0];
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9.80M
        ap[1] = v[1]; // Make sure we still have max min.
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9.80M
      }
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4
  ccv_float_to_half_precision(a->data.f32, (uint16_t*)a16->data.f16, N * C * H * W);
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4
  ccv_half_precision_to_float((uint16_t*)a16->data.f16, a->data.f32, N * C * H * W);
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4
  ccv_nnc_cmd_exec(CMD_COMPRESSION_LSSC_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(a16), TENSOR_LIST(b16), 0);
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4
  ccv_nnc_cmd_exec(CMD_COMPRESSION_LSSC_BACKWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(b16), TENSOR_LIST(c16), 0);
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4
  ccv_half_precision_to_float((uint16_t*)c16->data.f16, c->data.f32, N * C * H * W);
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4
  // Compare against GPU computation
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4
  ccv_nnc_tensor_param_t ag_params = GPU_TENSOR_NCHW(000, 16F, N, C, H, W);
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4
  ccv_nnc_tensor_t* const a16g = ccv_nnc_tensor_new(0, ag_params, 0);
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4
  ccv_nnc_tensor_param_t bg_params;
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4
  ccv_nnc_hint_tensor_auto(CMD_COMPRESSION_LSSC_FORWARD(), &ag_params, 1, ccv_nnc_no_hint, &bg_params, 1);
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4
  ccv_nnc_tensor_t* const b16g = ccv_nnc_tensor_new(0, bg_params, 0);
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4
  ccv_nnc_tensor_t* const c16g = ccv_nnc_tensor_new(0, ag_params, 0);
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4
  ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(a16), TENSOR_LIST(a16g), 0);
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4
  ccv_nnc_cmd_exec(CMD_COMPRESSION_LSSC_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(a16g), TENSOR_LIST(b16g), 0);
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4
  ccv_nnc_cmd_exec(CMD_COMPRESSION_LSSC_BACKWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(b16g), TENSOR_LIST(c16g), 0);
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4
  memset(c16->data.f16, 0, sizeof(ccv_float16_t) * N * C * H * W);
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4
  ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(c16g), TENSOR_LIST(c16), 0);
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4
  ccv_nnc_tensor_t* const cgc = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, N, C, H, W), 0);
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4
  ccv_half_precision_to_float((uint16_t*)c16->data.f16, cgc->data.f32, N * C * H * W);
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4
  *c_ptr = c;
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4
  *cgc_ptr = cgc;
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4
  ccv_nnc_tensor_free(a);
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4
  ccv_nnc_tensor_free(a16);
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4
  ccv_nnc_tensor_free(b16);
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4
  ccv_nnc_tensor_free(c16);
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4
  ccv_nnc_tensor_free(a16g);
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4
  ccv_nnc_tensor_free(b16g);
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4
  ccv_nnc_tensor_free(c16g);
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4
}
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TEST_CASE("LSSC should give exact result from GPU for 128x512x7x7")
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1
{
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1
  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_COMPRESSION_LSSC_FORWARD, CCV_NNC_BACKEND_GPU_REF) &&
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1
    ccv_nnc_cmd_ok(CCV_NNC_COMPRESSION_LSSC_BACKWARD, CCV_NNC_BACKEND_GPU_REF));
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1
  ccv_nnc_tensor_t* c;
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1
  ccv_nnc_tensor_t* cgc;
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1
  prepare_nchw(128, 512, 7, 7, &c, &cgc);
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1
  REQUIRE_ARRAY_EQ_WITH_TOLERANCE(float, c->data.f32, cgc->data.f32, 128 * 512 * 7 * 7, 1e-3, "GPU and CPU computed result should match");
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1
}
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TEST_CASE("LSSC should give exact result from GPU for 128x512x14x14")
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1
{
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1
  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_COMPRESSION_LSSC_FORWARD, CCV_NNC_BACKEND_GPU_REF) &&
87
1
    ccv_nnc_cmd_ok(CCV_NNC_COMPRESSION_LSSC_BACKWARD, CCV_NNC_BACKEND_GPU_REF));
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1
  ccv_nnc_tensor_t* c;
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1
  ccv_nnc_tensor_t* cgc;
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1
  prepare_nchw(128, 512, 14, 14, &c, &cgc);
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1
  REQUIRE_ARRAY_EQ_WITH_TOLERANCE(float, c->data.f32, cgc->data.f32, 128 * 512 * 14 * 14, 1e-3, "GPU and CPU computed result should match");
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1
}
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TEST_CASE("LSSC should give exact result from GPU for 128x64x113x114")
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1
{
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1
  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_COMPRESSION_LSSC_FORWARD, CCV_NNC_BACKEND_GPU_REF) &&
97
1
    ccv_nnc_cmd_ok(CCV_NNC_COMPRESSION_LSSC_BACKWARD, CCV_NNC_BACKEND_GPU_REF));
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1
  ccv_nnc_tensor_t* c;
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1
  ccv_nnc_tensor_t* cgc;
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1
  prepare_nchw(128, 64, 113, 114, &c, &cgc);
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1
  REQUIRE_ARRAY_EQ_WITH_TOLERANCE(float, c->data.f32, cgc->data.f32, 128 * 64 * 113 * 114, 1e-3, "GPU and CPU computed result should match");
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1
}
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TEST_CASE("LSSC should give exact result from GPU for 128x256x28x28")
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1
{
106
1
  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_COMPRESSION_LSSC_FORWARD, CCV_NNC_BACKEND_GPU_REF) &&
107
1
    ccv_nnc_cmd_ok(CCV_NNC_COMPRESSION_LSSC_BACKWARD, CCV_NNC_BACKEND_GPU_REF));
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1
  ccv_nnc_tensor_t* c;
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1
  ccv_nnc_tensor_t* cgc;
110
1
  prepare_nchw(128, 256, 28, 28, &c, &cgc);
111
1
  REQUIRE_ARRAY_EQ_WITH_TOLERANCE(float, c->data.f32, cgc->data.f32, 128 * 256 * 28 * 28, 1e-3, "GPU and CPU computed result should match");
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1
}
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114
#include "case_main.h"