Coverage Report

Created: 2021-04-06 03:49

/home/liu/buildslave/linux-x64-runtests/build/test/int/nnc/roi_align.tests.c
Line
Count
Source
1
#include "case.h"
2
#include "ccv_case.h"
3
#include "ccv_nnc_case.h"
4
#include <ccv.h>
5
#include <nnc/ccv_nnc.h>
6
#include <nnc/ccv_nnc_easy.h>
7
#include <3rdparty/dsfmt/dSFMT.h>
8
9
TEST_SETUP()
10
{
11
  ccv_nnc_init();
12
}
13
14
TEST_CASE("roi align forward with NCHW")
15
1
{
16
1
  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_ROI_ALIGN_FORWARD, CCV_NNC_BACKEND_GPU_REF) &&
17
1
    ccv_nnc_cmd_ok(CCV_NNC_ROI_ALIGN_BACKWARD, CCV_NNC_BACKEND_GPU_REF));
18
1
  ccv_nnc_tensor_t* const a = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, 128, 32, 32), 0);
19
1
  ccv_nnc_tensor_t* const b = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 4), 0);
20
1
  ccv_nnc_tensor_t* const c = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, 128, 4, 4), 0);
21
1
  ccv_nnc_tensor_t* const ha = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, 128, 32, 32), 0);
22
1
  ccv_nnc_tensor_t* const hb = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 4), 0);
23
1
  ccv_nnc_tensor_t* const hc = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, 128, 4, 4), 0);
24
1
  ccv_nnc_tensor_t* const hat = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 32, 32, 128), 0);
25
1
  ccv_nnc_tensor_t* const hcf = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 4, 4, 128), 0);
26
1
  ccv_nnc_tensor_t* const hct = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 4, 4, 128), 0);
27
1
  dsfmt_t dsfmt;
28
1
  dsfmt_init_gen_rand(&dsfmt, 0);
29
1
  int i;
30
131k
  for (i = 0; i < 32 * 32 * 128; 
i++131k
)
31
131k
    hat->data.f32[i] = dsfmt_genrand_open_close(&dsfmt);
32
1
  hb->data.f32[0] = 0 / 32;
33
1
  hb->data.f32[1] = 0 / 32;
34
1
  hb->data.f32[2] = 1;
35
1
  hb->data.f32[3] = 1;
36
1
  ccv_nnc_cmd_exec(CMD_FORMAT_TRANSFORM_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(hat), TENSOR_LIST(ha), 0);
37
1
  ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(ha, hb), TENSOR_LIST(a, b), 0);
38
1
  ccv_nnc_cmd_exec(CMD_ROI_ALIGN_FORWARD(4, 4), ccv_nnc_no_hint, 0, TENSOR_LIST(a, b), TENSOR_LIST(c), 0);
39
1
  ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(c), TENSOR_LIST(hc), 0);
40
1
  ccv_nnc_cmd_exec(CMD_FORMAT_TRANSFORM_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(hc), TENSOR_LIST(hcf), 0);
41
1
  ccv_nnc_cmd_exec(CMD_ROI_ALIGN_FORWARD(4, 4), ccv_nnc_no_hint, 0, TENSOR_LIST(hat, hb), TENSOR_LIST(hct), 0);
42
1
  REQUIRE_TENSOR_EQ(hct, hcf, "GPU computed output should be the same as CPU computed ones");
43
1
  ccv_nnc_tensor_free(a);
44
1
  ccv_nnc_tensor_free(b);
45
1
  ccv_nnc_tensor_free(c);
46
1
  ccv_nnc_tensor_free(ha);
47
1
  ccv_nnc_tensor_free(hb);
48
1
  ccv_nnc_tensor_free(hc);
49
1
  ccv_nnc_tensor_free(hat);
50
1
  ccv_nnc_tensor_free(hcf);
51
1
  ccv_nnc_tensor_free(hct);
52
1
}
53
54
TEST_CASE("roi align forward with NHWC")
55
1
{
56
1
  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_ROI_ALIGN_FORWARD, CCV_NNC_BACKEND_GPU_REF) &&
57
1
    ccv_nnc_cmd_ok(CCV_NNC_ROI_ALIGN_BACKWARD, CCV_NNC_BACKEND_GPU_REF));
58
1
  ccv_nnc_tensor_t* const a = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 32, 32, 128), 0);
59
1
  ccv_nnc_tensor_t* const b = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 4), 0);
60
1
  ccv_nnc_tensor_t* const c = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 4, 4, 128), 0);
61
1
  ccv_nnc_tensor_t* const ha = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 32, 32, 128), 0);
62
1
  ccv_nnc_tensor_t* const hb = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 4), 0);
63
1
  ccv_nnc_tensor_t* const hc = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 4, 4, 128), 0);
64
1
  ccv_nnc_tensor_t* const hct = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 4, 4, 128), 0);
65
1
  dsfmt_t dsfmt;
66
1
  dsfmt_init_gen_rand(&dsfmt, 0);
67
1
  int i;
68
131k
  for (i = 0; i < 32 * 32 * 128; 
i++131k
)
69
131k
    ha->data.f32[i] = dsfmt_genrand_open_close(&dsfmt);
70
1
  hb->data.f32[0] = 0 / 32;
71
1
  hb->data.f32[1] = 0 / 32;
72
1
  hb->data.f32[2] = 1;
73
1
  hb->data.f32[3] = 1;
74
1
  ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(ha, hb), TENSOR_LIST(a, b), 0);
75
1
  ccv_nnc_cmd_exec(CMD_ROI_ALIGN_FORWARD(4, 4), ccv_nnc_no_hint, 0, TENSOR_LIST(a, b), TENSOR_LIST(c), 0);
76
1
  ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(c), TENSOR_LIST(hc), 0);
77
1
  ccv_nnc_cmd_exec(CMD_ROI_ALIGN_FORWARD(4, 4), ccv_nnc_no_hint, 0, TENSOR_LIST(ha, hb), TENSOR_LIST(hct), 0);
78
1
  REQUIRE_TENSOR_EQ(hct, hc, "GPU computed output should be the same as CPU computed ones");
79
1
  ccv_nnc_tensor_free(a);
80
1
  ccv_nnc_tensor_free(b);
81
1
  ccv_nnc_tensor_free(c);
82
1
  ccv_nnc_tensor_free(ha);
83
1
  ccv_nnc_tensor_free(hb);
84
1
  ccv_nnc_tensor_free(hc);
85
1
  ccv_nnc_tensor_free(hct);
86
1
}
87
88
TEST_CASE("roi align forward with NCHW, batch of 2")
89
1
{
90
1
  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_ROI_ALIGN_FORWARD, CCV_NNC_BACKEND_GPU_REF) &&
91
1
    ccv_nnc_cmd_ok(CCV_NNC_ROI_ALIGN_BACKWARD, CCV_NNC_BACKEND_GPU_REF));
92
1
  ccv_nnc_tensor_t* const a = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, 2, 128, 32, 32), 0);
93
1
  ccv_nnc_tensor_t* const b = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 4), 0);
94
1
  ccv_nnc_tensor_t* const c = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, 2, 128, 4, 4), 0);
95
1
  ccv_nnc_tensor_t* const ha = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, 2, 128, 32, 32), 0);
96
1
  ccv_nnc_tensor_t* const hb = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 4), 0);
97
1
  ccv_nnc_tensor_t* const hc = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, 2, 128, 4, 4), 0);
98
1
  ccv_nnc_tensor_t* const hat = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 2, 32, 32, 128), 0);
99
1
  ccv_nnc_tensor_t* const hcf = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 2, 4, 4, 128), 0);
100
1
  ccv_nnc_tensor_t* const hct = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 2, 4, 4, 128), 0);
101
1
  dsfmt_t dsfmt;
102
1
  dsfmt_init_gen_rand(&dsfmt, 0);
103
1
  int i;
104
262k
  for (i = 0; i < 2 * 32 * 32 * 128; 
i++262k
)
105
262k
    hat->data.f32[i] = dsfmt_genrand_open_close(&dsfmt);
106
1
  hb->data.f32[0] = 0 / 32;
107
1
  hb->data.f32[1] = 0 / 32;
108
1
  hb->data.f32[2] = 1;
109
1
  hb->data.f32[3] = 1;
110
1
  ccv_nnc_cmd_exec(CMD_FORMAT_TRANSFORM_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(hat), TENSOR_LIST(ha), 0);
111
1
  ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(ha, hb), TENSOR_LIST(a, b), 0);
112
1
  ccv_nnc_cmd_exec(CMD_ROI_ALIGN_FORWARD(4, 4), ccv_nnc_no_hint, 0, TENSOR_LIST(a, b), TENSOR_LIST(c), 0);
113
1
  ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(c), TENSOR_LIST(hc), 0);
114
1
  ccv_nnc_cmd_exec(CMD_FORMAT_TRANSFORM_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(hc), TENSOR_LIST(hcf), 0);
115
1
  ccv_nnc_cmd_exec(CMD_ROI_ALIGN_FORWARD(4, 4), ccv_nnc_no_hint, 0, TENSOR_LIST(hat, hb), TENSOR_LIST(hct), 0);
116
1
  REQUIRE_TENSOR_EQ(hct, hcf, "GPU computed output should be the same as CPU computed ones");
117
1
  ccv_nnc_tensor_free(a);
118
1
  ccv_nnc_tensor_free(b);
119
1
  ccv_nnc_tensor_free(c);
120
1
  ccv_nnc_tensor_free(ha);
121
1
  ccv_nnc_tensor_free(hb);
122
1
  ccv_nnc_tensor_free(hc);
123
1
  ccv_nnc_tensor_free(hat);
124
1
  ccv_nnc_tensor_free(hcf);
125
1
  ccv_nnc_tensor_free(hct);
126
1
}
127
128
TEST_CASE("roi align forward with NHWC, batch of 2")
129
1
{
130
1
  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_ROI_ALIGN_FORWARD, CCV_NNC_BACKEND_GPU_REF) &&
131
1
    ccv_nnc_cmd_ok(CCV_NNC_ROI_ALIGN_BACKWARD, CCV_NNC_BACKEND_GPU_REF));
132
1
  ccv_nnc_tensor_t* const a = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 2, 32, 32, 128), 0);
133
1
  ccv_nnc_tensor_t* const b = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 2, 4), 0);
134
1
  ccv_nnc_tensor_t* const c = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 2, 4, 4, 128), 0);
135
1
  ccv_nnc_tensor_t* const ha = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 2, 32, 32, 128), 0);
136
1
  ccv_nnc_tensor_t* const hb = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 2, 4), 0);
137
1
  ccv_nnc_tensor_t* const hc = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 2, 4, 4, 128), 0);
138
1
  ccv_nnc_tensor_t* const hct = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 2, 4, 4, 128), 0);
139
1
  dsfmt_t dsfmt;
140
1
  dsfmt_init_gen_rand(&dsfmt, 0);
141
1
  int i;
142
262k
  for (i = 0; i < 2 * 32 * 32 * 128; 
i++262k
)
143
262k
    ha->data.f32[i] = dsfmt_genrand_open_close(&dsfmt);
144
1
  hb->data.f32[0] = 0 / 32;
145
1
  hb->data.f32[1] = 0 / 32;
146
1
  hb->data.f32[2] = 1;
147
1
  hb->data.f32[3] = 1;
148
1
  hb->data.f32[4] = 0 / 32;
149
1
  hb->data.f32[5] = 0 / 32;
150
1
  hb->data.f32[6] = 1;
151
1
  hb->data.f32[7] = 1;
152
1
  ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(ha, hb), TENSOR_LIST(a, b), 0);
153
1
  ccv_nnc_cmd_exec(CMD_ROI_ALIGN_FORWARD(4, 4), ccv_nnc_no_hint, 0, TENSOR_LIST(a, b), TENSOR_LIST(c), 0);
154
1
  ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(c), TENSOR_LIST(hc), 0);
155
1
  ccv_nnc_cmd_exec(CMD_ROI_ALIGN_FORWARD(4, 4), ccv_nnc_no_hint, 0, TENSOR_LIST(ha, hb), TENSOR_LIST(hct), 0);
156
1
  REQUIRE_TENSOR_EQ(hct, hc, "GPU computed output should be the same as CPU computed ones");
157
1
  ccv_nnc_tensor_free(a);
158
1
  ccv_nnc_tensor_free(b);
159
1
  ccv_nnc_tensor_free(c);
160
1
  ccv_nnc_tensor_free(ha);
161
1
  ccv_nnc_tensor_free(hb);
162
1
  ccv_nnc_tensor_free(hc);
163
1
  ccv_nnc_tensor_free(hct);
164
1
}
165
166
TEST_CASE("roi align backward with NCHW")
167
1
{
168
1
  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_ROI_ALIGN_FORWARD, CCV_NNC_BACKEND_GPU_REF) &&
169
1
    ccv_nnc_cmd_ok(CCV_NNC_ROI_ALIGN_BACKWARD, CCV_NNC_BACKEND_GPU_REF));
170
1
  ccv_nnc_tensor_t* const a = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, 128, 32, 32), 0);
171
1
  ccv_nnc_tensor_t* const b = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 4), 0);
172
1
  ccv_nnc_tensor_t* const c = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, 128, 4, 4), 0);
173
1
  ccv_nnc_tensor_t* const ha = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, 128, 32, 32), 0);
174
1
  ccv_nnc_tensor_t* const hb = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 4), 0);
175
1
  ccv_nnc_tensor_t* const hc = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, 128, 4, 4), 0);
176
1
  ccv_nnc_tensor_t* const hat = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 32, 32, 128), 0);
177
1
  ccv_nnc_tensor_t* const haf = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 32, 32, 128), 0);
178
1
  ccv_nnc_tensor_t* const hct = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 4, 4, 128), 0);
179
1
  dsfmt_t dsfmt;
180
1
  dsfmt_init_gen_rand(&dsfmt, 0);
181
1
  int i;
182
2.04k
  for (i = 0; i < 4 * 4 * 128; 
i++2.04k
)
183
2.04k
    hct->data.f32[i] = dsfmt_genrand_open_close(&dsfmt);
184
1
  hb->data.f32[0] = 0 / 32;
185
1
  hb->data.f32[1] = 0 / 32;
186
1
  hb->data.f32[2] = 1;
187
1
  hb->data.f32[3] = 1;
188
1
  ccv_nnc_cmd_exec(CMD_FORMAT_TRANSFORM_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(hct), TENSOR_LIST(hc), 0);
189
1
  ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(hc, hb), TENSOR_LIST(c, b), 0);
190
1
  ccv_nnc_cmd_exec(CMD_ROI_ALIGN_BACKWARD(4, 4), ccv_nnc_no_hint, 0, TENSOR_LIST(c, 0, b), TENSOR_LIST(a), 0);
191
1
  ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(a), TENSOR_LIST(ha), 0);
192
1
  ccv_nnc_cmd_exec(CMD_FORMAT_TRANSFORM_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(ha), TENSOR_LIST(haf), 0);
193
1
  ccv_nnc_cmd_exec(CMD_ROI_ALIGN_BACKWARD(4, 4), ccv_nnc_no_hint, 0, TENSOR_LIST(hct, 0, hb), TENSOR_LIST(hat), 0);
194
1
  REQUIRE_TENSOR_EQ(hat, haf, "GPU computed output should be the same as CPU computed ones");
195
1
  ccv_nnc_tensor_free(a);
196
1
  ccv_nnc_tensor_free(b);
197
1
  ccv_nnc_tensor_free(c);
198
1
  ccv_nnc_tensor_free(ha);
199
1
  ccv_nnc_tensor_free(hb);
200
1
  ccv_nnc_tensor_free(hc);
201
1
  ccv_nnc_tensor_free(hat);
202
1
  ccv_nnc_tensor_free(haf);
203
1
  ccv_nnc_tensor_free(hct);
204
1
}
205
206
TEST_CASE("roi align backward with NHWC")
207
1
{
208
1
  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_ROI_ALIGN_FORWARD, CCV_NNC_BACKEND_GPU_REF) &&
209
1
    ccv_nnc_cmd_ok(CCV_NNC_ROI_ALIGN_BACKWARD, CCV_NNC_BACKEND_GPU_REF));
210
1
  ccv_nnc_tensor_t* const a = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 32, 32, 128), 0);
211
1
  ccv_nnc_tensor_t* const b = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 4), 0);
212
1
  ccv_nnc_tensor_t* const c = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 4, 4, 128), 0);
213
1
  ccv_nnc_tensor_t* const ha = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 32, 32, 128), 0);
214
1
  ccv_nnc_tensor_t* const hb = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 4), 0);
215
1
  ccv_nnc_tensor_t* const hc = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 4, 4, 128), 0);
216
1
  ccv_nnc_tensor_t* const hat = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 32, 32, 128), 0);
217
1
  dsfmt_t dsfmt;
218
1
  dsfmt_init_gen_rand(&dsfmt, 0);
219
1
  int i;
220
2.04k
  for (i = 0; i < 4 * 4 * 128; 
i++2.04k
)
221
2.04k
    hc->data.f32[i] = dsfmt_genrand_open_close(&dsfmt);
222
1
  hb->data.f32[0] = 0 / 32;
223
1
  hb->data.f32[1] = 0 / 32;
224
1
  hb->data.f32[2] = 1;
225
1
  hb->data.f32[3] = 1;
226
1
  ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(hc, hb), TENSOR_LIST(c, b), 0);
227
1
  ccv_nnc_cmd_exec(CMD_ROI_ALIGN_BACKWARD(4, 4), ccv_nnc_no_hint, 0, TENSOR_LIST(c, 0, b), TENSOR_LIST(a), 0);
228
1
  ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(a), TENSOR_LIST(ha), 0);
229
1
  ccv_nnc_cmd_exec(CMD_ROI_ALIGN_BACKWARD(4, 4), ccv_nnc_no_hint, 0, TENSOR_LIST(hc, 0, hb), TENSOR_LIST(hat), 0);
230
1
  REQUIRE_TENSOR_EQ(hat, ha, "GPU computed output should be the same as CPU computed ones");
231
1
  ccv_nnc_tensor_free(a);
232
1
  ccv_nnc_tensor_free(b);
233
1
  ccv_nnc_tensor_free(c);
234
1
  ccv_nnc_tensor_free(ha);
235
1
  ccv_nnc_tensor_free(hb);
236
1
  ccv_nnc_tensor_free(hc);
237
1
  ccv_nnc_tensor_free(hat);
238
1
}
239
240
TEST_CASE("roi align backward with NCHW, batch of 2")
241
1
{
242
1
  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_ROI_ALIGN_FORWARD, CCV_NNC_BACKEND_GPU_REF) &&
243
1
    ccv_nnc_cmd_ok(CCV_NNC_ROI_ALIGN_BACKWARD, CCV_NNC_BACKEND_GPU_REF));
244
1
  ccv_nnc_tensor_t* const a = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, 2, 128, 32, 32), 0);
245
1
  ccv_nnc_tensor_t* const b = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 4), 0);
246
1
  ccv_nnc_tensor_t* const c = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, 2, 128, 4, 4), 0);
247
1
  ccv_nnc_tensor_t* const ha = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, 2, 128, 32, 32), 0);
248
1
  ccv_nnc_tensor_t* const hb = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 4), 0);
249
1
  ccv_nnc_tensor_t* const hc = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, 2, 128, 4, 4), 0);
250
1
  ccv_nnc_tensor_t* const hat = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 2, 32, 32, 128), 0);
251
1
  ccv_nnc_tensor_t* const haf = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 2, 32, 32, 128), 0);
252
1
  ccv_nnc_tensor_t* const hct = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 2, 4, 4, 128), 0);
253
1
  dsfmt_t dsfmt;
254
1
  dsfmt_init_gen_rand(&dsfmt, 0);
255
1
  int i;
256
4.09k
  for (i = 0; i < 2 * 4 * 4 * 128; 
i++4.09k
)
257
4.09k
    hct->data.f32[i] = dsfmt_genrand_open_close(&dsfmt);
258
1
  hb->data.f32[0] = 0 / 32;
259
1
  hb->data.f32[1] = 0 / 32;
260
1
  hb->data.f32[2] = 1;
261
1
  hb->data.f32[3] = 1;
262
1
  ccv_nnc_cmd_exec(CMD_FORMAT_TRANSFORM_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(hct), TENSOR_LIST(hc), 0);
263
1
  ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(hc, hb), TENSOR_LIST(c, b), 0);
264
1
  ccv_nnc_cmd_exec(CMD_ROI_ALIGN_BACKWARD(4, 4), ccv_nnc_no_hint, 0, TENSOR_LIST(c, 0, b), TENSOR_LIST(a), 0);
265
1
  ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(a), TENSOR_LIST(ha), 0);
266
1
  ccv_nnc_cmd_exec(CMD_FORMAT_TRANSFORM_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(ha), TENSOR_LIST(haf), 0);
267
1
  ccv_nnc_cmd_exec(CMD_ROI_ALIGN_BACKWARD(4, 4), ccv_nnc_no_hint, 0, TENSOR_LIST(hct, 0, hb), TENSOR_LIST(hat), 0);
268
1
  REQUIRE_TENSOR_EQ(hat, haf, "GPU computed output should be the same as CPU computed ones");
269
1
  ccv_nnc_tensor_free(a);
270
1
  ccv_nnc_tensor_free(b);
271
1
  ccv_nnc_tensor_free(c);
272
1
  ccv_nnc_tensor_free(ha);
273
1
  ccv_nnc_tensor_free(hb);
274
1
  ccv_nnc_tensor_free(hc);
275
1
  ccv_nnc_tensor_free(hat);
276
1
  ccv_nnc_tensor_free(haf);
277
1
  ccv_nnc_tensor_free(hct);
278
1
}
279
280
TEST_CASE("roi align backward with NHWC, batch of 2")
281
1
{
282
1
  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_ROI_ALIGN_FORWARD, CCV_NNC_BACKEND_GPU_REF) &&
283
1
    ccv_nnc_cmd_ok(CCV_NNC_ROI_ALIGN_BACKWARD, CCV_NNC_BACKEND_GPU_REF));
284
1
  ccv_nnc_tensor_t* const a = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 2, 32, 32, 128), 0);
285
1
  ccv_nnc_tensor_t* const b = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 2, 4), 0);
286
1
  ccv_nnc_tensor_t* const c = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 2, 4, 4, 128), 0);
287
1
  ccv_nnc_tensor_t* const ha = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 2, 32, 32, 128), 0);
288
1
  ccv_nnc_tensor_t* const hb = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 2, 4), 0);
289
1
  ccv_nnc_tensor_t* const hc = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 2, 4, 4, 128), 0);
290
1
  ccv_nnc_tensor_t* const hat = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 2, 32, 32, 128), 0);
291
1
  dsfmt_t dsfmt;
292
1
  dsfmt_init_gen_rand(&dsfmt, 0);
293
1
  int i;
294
4.09k
  for (i = 0; i < 2 * 4 * 4 * 128; 
i++4.09k
)
295
4.09k
    hc->data.f32[i] = dsfmt_genrand_open_close(&dsfmt);
296
1
  hb->data.f32[0] = 0 / 32;
297
1
  hb->data.f32[1] = 0 / 32;
298
1
  hb->data.f32[2] = 1;
299
1
  hb->data.f32[3] = 1;
300
1
  hb->data.f32[4] = 0 / 32;
301
1
  hb->data.f32[5] = 0 / 32;
302
1
  hb->data.f32[6] = 1;
303
1
  hb->data.f32[7] = 1;
304
1
  ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(hc, hb), TENSOR_LIST(c, b), 0);
305
1
  ccv_nnc_cmd_exec(CMD_ROI_ALIGN_BACKWARD(4, 4), ccv_nnc_no_hint, 0, TENSOR_LIST(c, 0, b), TENSOR_LIST(a), 0);
306
1
  ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(a), TENSOR_LIST(ha), 0);
307
1
  ccv_nnc_cmd_exec(CMD_ROI_ALIGN_BACKWARD(4, 4), ccv_nnc_no_hint, 0, TENSOR_LIST(hc, 0, hb), TENSOR_LIST(hat), 0);
308
1
  REQUIRE_TENSOR_EQ(hat, ha, "GPU computed output should be the same as CPU computed ones");
309
1
  ccv_nnc_tensor_free(a);
310
1
  ccv_nnc_tensor_free(b);
311
1
  ccv_nnc_tensor_free(c);
312
1
  ccv_nnc_tensor_free(ha);
313
1
  ccv_nnc_tensor_free(hb);
314
1
  ccv_nnc_tensor_free(hc);
315
1
  ccv_nnc_tensor_free(hat);
316
1
}
317
318
#include "case_main.h"