Coverage Report

Created: 2021-04-12 01:11

/home/liu/buildslave/linux-x64-runtests/build/lib/nnc/cmd/rmsprop/ccv_nnc_rmsprop.c
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Source (jump to first uncovered line)
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#include "ccv.h"
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#include "nnc/ccv_nnc.h"
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#include "nnc/ccv_nnc_internal.h"
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static int _ccv_nnc_rmsprop_forw_bitmask(const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  // 4 inputs (gradient, x, momentum, squared gradient average)
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  // 3 outputs (y, new momentum, new squared gradient average)
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  if (input_bitmasks[0] == 15u && 
output_bitmasks[0] == 7u1
)
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    return 1;
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  return 0;
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}
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static int _ccv_nnc_rmsprop_allow_inplace(const int input_idx, const int input_size, const int output_idx, const int output_size)
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{
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  if (input_idx == output_idx + 1)
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    return 1;
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  return 0;
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}
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static int _ccv_nnc_rmsprop_back_bitmask(const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  // Doesn't support.
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  return 0;
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}
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static void _ccv_nnc_rmsprop_tensor_auto_forw(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* const inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* const outputs, const int output_size)
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{
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  int i;
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  for (i = 0; i < output_size; 
i++3
)
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    outputs[i] = inputs[0];
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}
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static void _ccv_nnc_rmsprop_tensor_auto_back(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* const inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* const outputs, const int output_size)
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{
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  // Doesn't support.
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}
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REGISTER_COMMAND(CCV_NNC_RMSPROP_FORWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_rmsprop_cpu_ref.c, gpu/ccv_nnc_rmsprop_gpu_ref.cu)
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{
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  registry->bitmask = _ccv_nnc_rmsprop_forw_bitmask;
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  registry->tensor_auto = _ccv_nnc_rmsprop_tensor_auto_forw;
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  registry->allow_inplace = _ccv_nnc_rmsprop_allow_inplace;
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}
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REGISTER_COMMAND(CCV_NNC_RMSPROP_BACKWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_rmsprop_cpu_ref.c, gpu/ccv_nnc_rmsprop_gpu_ref.cu)
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{
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  registry->bitmask = _ccv_nnc_rmsprop_back_bitmask;
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  registry->tensor_auto = _ccv_nnc_rmsprop_tensor_auto_back;
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}
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//@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_RMSPROP_FORWARD)
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#define CMD_RMSPROP_FORWARD(_rate, _decay, _alpha, _momentum, _epsilon) ccv_nnc_cmd(CCV_NNC_RMSPROP_FORWARD, 0, ((ccv_nnc_cmd_param_t){.size={.dim={1,1,1}},.rmsprop={.rate=_rate,.decay=_decay,.alpha=_alpha,.momentum=_momentum,.epsilon=_epsilon}}), 0)