Coverage Report

Created: 2021-04-14 15:26

/home/liu/buildslave/linux-x64-runtests/build/lib/nnc/cmd/sigmoid/ccv_nnc_sigmoid.c
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Source (jump to first uncovered line)
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#include "ccv.h"
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#include "nnc/ccv_nnc.h"
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#include "nnc/ccv_nnc_easy.h"
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#include "nnc/ccv_nnc_internal.h"
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static int _ccv_nnc_sigmoid_allow_first_replace(const int input_idx, const int input_size, const int output_idx, const int output_size)
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{
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  return input_idx == 0 && 
output_idx == 08
;
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}
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static int _ccv_nnc_sigmoid_forw_bitmask(const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  if ((input_bitmasks[0] & 1u) == 1u && output_bitmasks[0] == 1u)
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    return 1;
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  return 0;
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}
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static int _ccv_nnc_sigmoid_back_bitmask(const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  // gradient, [x], y
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  if ((input_bitmasks[0] & 5u) == 5u && 
(output_bitmasks[0] & 1u) == 1u10
)
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    return 1;
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  return 0;
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}
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static void _ccv_nnc_sigmoid_tensor_auto_forw(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* const inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* const outputs, const int output_size)
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{
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  assert(input_size == 1);
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  assert(output_size == 1);
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  outputs[0] = inputs[0];
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}
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static void _ccv_nnc_sigmoid_tensor_auto_back(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* const inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* const outputs, const int output_size)
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{
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  assert(input_size >= 3);
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  assert(output_size >= 1);
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  outputs[0] = inputs[2];
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}
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REGISTER_COMMAND(CCV_NNC_SIGMOID_FORWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_sigmoid_cpu_ref.c, gpu/ccv_nnc_sigmoid_gpu_cudnn.cu)
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{
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  registry->bitmask = _ccv_nnc_sigmoid_forw_bitmask;
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  registry->allow_inplace = _ccv_nnc_sigmoid_allow_first_replace;
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  registry->tensor_auto = _ccv_nnc_sigmoid_tensor_auto_forw;
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}
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REGISTER_COMMAND(CCV_NNC_SIGMOID_BACKWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_sigmoid_cpu_ref.c, gpu/ccv_nnc_sigmoid_gpu_cudnn.cu)
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{
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  registry->flags = CCV_NNC_CMD_ATTR_NULL_IS_ONES;
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  registry->bitmask = _ccv_nnc_sigmoid_back_bitmask;
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  registry->allow_inplace = _ccv_nnc_sigmoid_allow_first_replace;
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  registry->tensor_auto = _ccv_nnc_sigmoid_tensor_auto_back;
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}
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//@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_SIGMOID_FORWARD)
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#define CMD_SIGMOID_FORWARD() ccv_nnc_cmd(CCV_NNC_SIGMOID_FORWARD, 0, ccv_nnc_cmd_auto, 0)
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//@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_SIGMOID_BACKWARD)
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#define CMD_SIGMOID_BACKWARD() ccv_nnc_cmd(CCV_NNC_SIGMOID_BACKWARD, 0, ccv_nnc_cmd_auto, 0)