Coverage Report

Created: 2021-09-30 21:42

/home/liu/buildslave/linux-x64-runtests/build/lib/nnc/cmd/nms/ccv_nnc_nms.c
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#include "ccv.h"
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#include "nnc/ccv_nnc.h"
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#include "nnc/ccv_nnc_easy.h"
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#include "nnc/ccv_nnc_internal.h"
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static int _ccv_nnc_nms_forw_bitmask(const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  if ((input_bitmasks[0] & 1u) == 1u && output_bitmasks[0] == 3u)
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    return 1;
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  return 0;
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}
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static int _ccv_nnc_nms_back_bitmask(const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  // gradient of sorted, gradient of sorting index, input, output of sorted, output of sorting index.
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  if ((input_bitmasks[0] & 17u) == ((1u << 0) | (0u << 1) | (0u << 2) | (0u << 3) | (1u << 4)) && output_bitmasks[0] == 1u)
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    return 1;
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  return 0;
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}
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static void _ccv_nnc_nms_tensor_auto_forw(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* outputs, const int output_size)
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{
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  assert(output_size == 2);
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  outputs[0] = inputs[0];
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  const int nd = ccv_nnc_tensor_nd(inputs[0].dim);
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  assert(nd >= 1);
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  outputs[1] = inputs[0];
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  outputs[1].datatype = CCV_32S;
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  memset(outputs[1].dim, 0, sizeof(outputs[1].dim));
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  outputs[1].dim[0] = inputs[0].dim[0]; // How many to rank (or batch size).
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  outputs[1].dim[1] = (nd <= 2) ? 0 : inputs[0].dim[1]; // How many to rank.
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}
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static void _ccv_nnc_nms_tensor_auto_back(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* outputs, const int output_size)
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{
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  assert(output_size == 1);
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  outputs[0] = inputs[2];
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}
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REGISTER_COMMAND(CCV_NNC_NMS_FORWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_nms_cpu_ref.c, gpu/ccv_nnc_nms_gpu_ref.cu)
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{
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  registry->bitmask = _ccv_nnc_nms_forw_bitmask;
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  registry->tensor_auto = _ccv_nnc_nms_tensor_auto_forw;
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}
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REGISTER_COMMAND(CCV_NNC_NMS_BACKWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_nms_cpu_ref.c, gpu/ccv_nnc_nms_gpu_ref.cu)
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{
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  registry->bitmask = _ccv_nnc_nms_back_bitmask;
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  registry->tensor_auto = _ccv_nnc_nms_tensor_auto_back;
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}
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//@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_NMS_FORWARD)
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#define CMD_NMS_FORWARD(_iou_threshold) ccv_nnc_cmd(CCV_NNC_NMS_FORWARD, 0, ((ccv_nnc_cmd_param_t){.nms={.iou_threshold=_iou_threshold}}), 0)
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//@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_NMS_BACKWARD)
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#define CMD_NMS_BACKWARD(_iou_threshold) ccv_nnc_cmd(CCV_NNC_NMS_BACKWARD, 0, ((ccv_nnc_cmd_param_t){.nms={.iou_threshold=_iou_threshold}}), 0)