Coverage Report

Created: 2021-10-28 19:33

/home/liu/buildslave/linux-x64-runtests/build/lib/nnc/cmd/reduce/ccv_nnc_reduce.c
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Source (jump to first uncovered line)
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#include "ccv.h"
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#include "nnc/ccv_nnc.h"
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#include "nnc/ccv_nnc_internal.h"
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static void _ccv_nnc_reduce_tensor_auto_forw(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* const inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* const outputs, const int output_size)
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{
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  assert(input_size == 1);
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  assert(output_size == 1);
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  outputs[0] = inputs[0];
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  int i;
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  for (i = 0; i < cmd.reduce.count; 
i++8.06k
)
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    outputs[0].dim[cmd.reduce.axis[i]] = 1; // Reduce the dimension to 1.
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}
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static int _ccv_nnc_reduce_sum_forw_bitmask(const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  if (input_bitmasks[0] == 1u && 
output_bitmasks[0] == 1u2
)
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    return 1;
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  return 0;
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}
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static int _ccv_nnc_reduce_sum_back_bitmask(const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  // Output the propagated error.
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  if ((input_bitmasks[0] & 1u) == 1u && 
output_bitmasks[0] == 1u6.02k
)
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    return 1;
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  return 0;
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}
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REGISTER_COMMAND(CCV_NNC_REDUCE_SUM_FORWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_reduce_sum_cpu_ref.c, gpu/ccv_nnc_reduce_sum_gpu_cudnn.cu)
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{
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  registry->bitmask = _ccv_nnc_reduce_sum_forw_bitmask;
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  registry->tensor_auto = _ccv_nnc_reduce_tensor_auto_forw;
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}
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REGISTER_COMMAND(CCV_NNC_REDUCE_SUM_BACKWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_reduce_sum_cpu_ref.c, gpu/ccv_nnc_reduce_sum_gpu_cudnn.cu)
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{
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  registry->bitmask = _ccv_nnc_reduce_sum_back_bitmask;
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  registry->tensor_auto = ccv_nnc_hint_tensor_auto_backward_from_gradient;
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}
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//@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_REDUCE_SUM_FORWARD)
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#define CMD_REDUCE_SUM_FORWARD(...) ccv_nnc_cmd(CCV_NNC_REDUCE_SUM_FORWARD, 0, CMD_REDUCE(__VA_ARGS__), 0)
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//@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_REDUCE_SUM_BACKWARD)
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#define CMD_REDUCE_SUM_BACKWARD(...) ccv_nnc_cmd(CCV_NNC_REDUCE_SUM_BACKWARD, 0, CMD_REDUCE(__VA_ARGS__), 0)
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static int _ccv_nnc_reduce_max_forw_bitmask(const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  if (input_bitmasks[0] == 1u && 
output_bitmasks[0] == 1u2
)
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    return 1;
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  return 0;
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}
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static int _ccv_nnc_reduce_max_back_bitmask(const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  // Output the propagated error.
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  if ((input_bitmasks[0] & 7u) == 7u && 
output_bitmasks[0] == 1u1
)
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    return 1;
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  return 0;
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}
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REGISTER_COMMAND(CCV_NNC_REDUCE_MAX_FORWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_reduce_max_cpu_ref.c)
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{
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  registry->bitmask = _ccv_nnc_reduce_max_forw_bitmask;
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  registry->tensor_auto = _ccv_nnc_reduce_tensor_auto_forw;
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}
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REGISTER_COMMAND(CCV_NNC_REDUCE_MAX_BACKWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_reduce_max_cpu_ref.c)
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{
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  registry->bitmask = _ccv_nnc_reduce_max_back_bitmask;
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  registry->tensor_auto = ccv_nnc_hint_tensor_auto_backward_from_gradient;
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}
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//@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_REDUCE_MAX_FORWARD)
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#define CMD_REDUCE_MAX_FORWARD(...) ccv_nnc_cmd(CCV_NNC_REDUCE_MAX_FORWARD, 0, CMD_REDUCE(__VA_ARGS__), 0)
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//@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_REDUCE_MAX_BACKWARD)
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#define CMD_REDUCE_MAX_BACKWARD(...) ccv_nnc_cmd(CCV_NNC_REDUCE_MAX_BACKWARD, 0, CMD_REDUCE(__VA_ARGS__), 0)
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static int _ccv_nnc_argmax_forw_bitmask(const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  if (input_bitmasks[0] == 1u && output_bitmasks[0] == 1u)
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    return 1;
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  return 0;
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}
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static int _ccv_nnc_argmax_back_bitmask(const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
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{
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  // Doesn't support.
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  return 0;
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}
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static void _ccv_nnc_argmax_tensor_auto_forw(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* const inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* const outputs, const int output_size)
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{
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  assert(input_size == 1);
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  assert(output_size == 1);
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  outputs[0] = inputs[0];
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  int i;
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  for (i = 0; i < cmd.reduce.count; i++)
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    outputs[0].dim[cmd.reduce.axis[i]] = 1; // Reduce the dimension to 1.
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  outputs[0].type = CCV_32S;
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}
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static void _ccv_nnc_argmax_tensor_auto_back(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* const inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* const outputs, const int output_size)
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{
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  // Doesn't support.
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}
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REGISTER_COMMAND(CCV_NNC_ARGMAX_FORWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_argmax_cpu_ref.c, gpu/ccv_nnc_argmax_gpu_ref.cu)
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{
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  registry->bitmask = _ccv_nnc_argmax_forw_bitmask;
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  registry->tensor_auto = _ccv_nnc_argmax_tensor_auto_forw;
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}
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REGISTER_COMMAND(CCV_NNC_ARGMAX_BACKWARD)(ccv_nnc_cmd_registry_t* const registry)
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  FIND_BACKEND(ccv_nnc_argmax_cpu_ref.c, gpu/ccv_nnc_argmax_gpu_ref.cu)
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{
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  registry->bitmask = _ccv_nnc_argmax_back_bitmask;
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  registry->tensor_auto = _ccv_nnc_argmax_tensor_auto_back;
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}
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//@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_ARGMAX_FORWARD)
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#define CMD_ARGMAX_FORWARD(...) ccv_nnc_cmd(CCV_NNC_ARGMAX_FORWARD, 0, CMD_REDUCE(__VA_ARGS__), 0)
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//@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_ARGMAX_BACKWARD)
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#define CMD_ARGMAX_BACKWARD(...) ccv_nnc_cmd(CCV_NNC_ARGMAX_BACKWARD, 0, CMD_REDUCE(__VA_ARGS__), 0)