Coverage Report

Created: 2024-08-19 11:27

/home/liu/actions-runner/_work/ccv/ccv/lib/nnc/cmd/isnan/ccv_nnc_reduce_isnan_cpu_ref.c
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Source (jump to first uncovered line)
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#include "ccv.h"
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#include "ccv_internal.h"
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#include "nnc/ccv_nnc.h"
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#include "nnc/ccv_nnc_easy.h"
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#include "nnc/ccv_nnc_internal.h"
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#ifdef USE_OPENMP
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#include <omp.h>
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#endif
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#ifdef USE_DISPATCH
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#include <dispatch/dispatch.h>
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#endif
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// Shared methods.
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#include "../_ccv_nnc_cpu_ref.h"
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static int _ccv_nnc_reduce_isnan_forw(const ccv_nnc_cmd_t cmd, const ccv_nnc_hint_t hint, const int flags, ccv_nnc_tensor_t* const* const inputs, const int input_size, ccv_nnc_tensor_t* const* const outputs, const int output_size, ccv_nnc_stream_context_t* const stream_context)
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{
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  assert(input_size == 1);
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  ccv_nnc_tensor_view_t* const a = (ccv_nnc_tensor_view_t*)inputs[0];
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  ccv_nnc_tensor_view_t* const b = (ccv_nnc_tensor_view_t*)outputs[0];
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  assert(ccv_nnc_tensor_nd(a->info.dim) <= CCV_NNC_MAX_DIM + 2);
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  assert(ccv_nnc_tensor_nd(b->info.dim) <= CCV_NNC_MAX_DIM + 2);
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  // Assuming this is float 32.
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  int adim[CCV_NNC_MAX_DIM_ALLOC];
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  int bdim[CCV_NNC_MAX_DIM_ALLOC];
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  ccv_nnc_tensor_view_get_dim(a, adim);
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  ccv_nnc_tensor_view_get_dim(b, bdim);
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  assert(ccv_nnc_tensor_view_check_broadcast_dim(b, adim));
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  int astride[CCV_NNC_MAX_DIM_ALLOC];
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  int bstride[CCV_NNC_MAX_DIM_ALLOC];
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  assert(CCV_NNC_MAX_DIM == 2); // Need to change this logic for CCV_NNC_MAX_DIM == other number.
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  ccv_nnc_tensor_view_get_stride(a, astride);
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  ccv_nnc_tensor_view_get_stride(b, bstride);
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  int i[CCV_NNC_MAX_DIM + 2];
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  int x;
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  _ccv_nnc_tensor_set_cpu_ref_i32(b, 0);
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  float* const ap = a->data.f32;
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  int* const bp = b->data.i32;
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  // Non-optimal case, need to do skip if needed.
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  for (i[0] = 0; i[0] < adim[0]; 
i[0]++3
)
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  {
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    float* const ap0 = ap + i[0] * astride[0];
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    int* const bp0 = bdim[0] == 1 ? bp : 
bp + i[0] * bstride[0]0
;
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    for (i[1] = 0; i[1] < adim[1]; 
i[1]++3
)
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    {
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      float* ap1 = ap0 + i[1] * astride[1];
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      int* const bp1 = bdim[1] == 1 ? bp0 : 
bp0 + i[1] * bstride[1]0
;
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      for (i[2] = 0; i[2] < adim[2]; 
i[2]++6
)
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      {
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        int* const bp2 = bdim[2] == 1 ? 
bp14
 : 
bp1 + i[2] * bstride[2]2
;
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        if (bdim[3] == 1)
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        {
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          for (x = 0; x < adim[3]; 
x++12
)
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            if (isnan(ap1[x]))
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              bp2[0] = 1;
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        } else {
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          for (x = 0; x < adim[3]; 
x++6
)
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            if (isnan(ap1[x]))
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              bp2[x] = 1;
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        }
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        ap1 += astride[2];
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      }
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    }
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  }
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  return CCV_NNC_EXEC_SUCCESS;
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}
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static int _ccv_nnc_reduce_isnan_back(const ccv_nnc_cmd_t cmd, const ccv_nnc_hint_t hint, const int flags, ccv_nnc_tensor_t* const* const inputs, const int input_size, ccv_nnc_tensor_t* const* const outputs, const int output_size, ccv_nnc_stream_context_t* const stream_context)
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{
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  return CCV_NNC_EXEC_INVALID;
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}
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REGISTER_COMMAND_BACKEND(CCV_NNC_REDUCE_ISNAN_FORWARD, CCV_NNC_BACKEND_CPU_REF)(ccv_nnc_cmd_backend_registry_t* const registry)
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{
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  registry->tensor_formats = CCV_TENSOR_FORMAT_NHWC | CCV_TENSOR_FORMAT_NCHW | CCV_TENSOR_FORMAT_CHWN;
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  registry->tensor_datatypes = CCV_32F | CCV_32S;
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  registry->tensor_memory = CCV_TENSOR_CPU_MEMORY;
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  registry->algorithms = 1;
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  registry->exec = _ccv_nnc_reduce_isnan_forw;
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}
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REGISTER_COMMAND_BACKEND(CCV_NNC_REDUCE_ISNAN_BACKWARD, CCV_NNC_BACKEND_CPU_REF)(ccv_nnc_cmd_backend_registry_t* const registry)
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{
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  registry->tensor_formats = CCV_TENSOR_FORMAT_NHWC | CCV_TENSOR_FORMAT_NCHW | CCV_TENSOR_FORMAT_CHWN;
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  registry->tensor_datatypes = CCV_32F | CCV_32S;
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  registry->tensor_memory = CCV_TENSOR_CPU_MEMORY;
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  registry->algorithms = 1;
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  registry->exec = _ccv_nnc_reduce_isnan_back;
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}