/home/liu/actions-runner/_work/ccv/ccv/test/int/nnc/index.tests.c
Line | Count | Source |
1 | | #include "case.h" |
2 | | #include "ccv_case.h" |
3 | | #include "ccv_nnc_case.h" |
4 | | #include <ccv.h> |
5 | | #include <nnc/ccv_nnc.h> |
6 | | #include <nnc/ccv_nnc_easy.h> |
7 | | #include <3rdparty/dsfmt/dSFMT.h> |
8 | | |
9 | | TEST_SETUP() |
10 | | { |
11 | | ccv_nnc_init(); |
12 | | } |
13 | | |
14 | | TEST_CASE("index select a tensor") |
15 | 1 | { |
16 | 1 | GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_INDEX_SELECT_FORWARD, CCV_NNC_BACKEND_GPU_REF) || ccv_nnc_cmd_ok(CCV_NNC_INDEX_SELECT_FORWARD, CCV_NNC_BACKEND_MPS)); |
17 | 1 | float ap[] = { |
18 | 1 | 1, 2, |
19 | 1 | 2, 3, |
20 | 1 | 3, 4, |
21 | 1 | }; |
22 | 1 | ccv_nnc_tensor_t* const a = ccv_nnc_tensor_new(ap, CPU_TENSOR_NHWC(32F, 3, 2), 0); |
23 | 1 | int ip[] = {1, 1}; |
24 | 1 | ccv_nnc_tensor_t* const indices = ccv_nnc_tensor_new(ip, CPU_TENSOR_NHWC(32S, 2), 0); |
25 | 1 | ccv_nnc_tensor_t* const b = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 2, 2), 0); |
26 | 1 | ccv_nnc_tensor_t* const ga = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 3, 2), 0); |
27 | 1 | ccv_nnc_tensor_t* const gindices = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32S, 2), 0); |
28 | 1 | ccv_nnc_tensor_t* const gb = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 2, 2), 0); |
29 | 1 | ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(a, indices), TENSOR_LIST(ga, gindices), 0); |
30 | 1 | ccv_nnc_cmd_exec(CMD_INDEX_SELECT_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(ga, gindices), TENSOR_LIST(gb), 0); |
31 | 1 | ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(gb), TENSOR_LIST(b), 0); |
32 | 1 | float btp[] = { |
33 | 1 | 2, 3, |
34 | 1 | 2, 3, |
35 | 1 | }; |
36 | 1 | ccv_nnc_tensor_t const bt = ccv_nnc_tensor(btp, CPU_TENSOR_NHWC(32F, 2, 2), 0); |
37 | 1 | REQUIRE_TENSOR_EQ(b, &bt, "should be equal"); |
38 | 1 | ccv_nnc_tensor_free(a); |
39 | 1 | ccv_nnc_tensor_free(indices); |
40 | 1 | ccv_nnc_tensor_free(b); |
41 | 1 | ccv_nnc_tensor_free(ga); |
42 | 1 | ccv_nnc_tensor_free(gindices); |
43 | 1 | ccv_nnc_tensor_free(gb); |
44 | 1 | } |
45 | | |
46 | | TEST_CASE("index select a tensor with float") |
47 | 1 | { |
48 | 1 | GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_INDEX_SELECT_FORWARD, CCV_NNC_BACKEND_GPU_REF) || ccv_nnc_cmd_ok(CCV_NNC_INDEX_SELECT_FORWARD, CCV_NNC_BACKEND_MPS)); |
49 | 1 | float ap[] = { |
50 | 1 | 1, 2, |
51 | 1 | 2, 3, |
52 | 1 | 3, 4, |
53 | 1 | }; |
54 | 1 | ccv_nnc_tensor_t* const a = ccv_nnc_tensor_new(ap, CPU_TENSOR_NHWC(32F, 3, 2), 0); |
55 | 1 | float ip[] = {1.5, 0.4}; |
56 | 1 | ccv_nnc_tensor_t* const indices = ccv_nnc_tensor_new(ip, CPU_TENSOR_NHWC(32F, 2), 0); |
57 | 1 | ccv_nnc_tensor_t* const b = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 2, 2), 0); |
58 | 1 | ccv_nnc_tensor_t* const ga = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 3, 2), 0); |
59 | 1 | ccv_nnc_tensor_t* const gindices = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 2), 0); |
60 | 1 | ccv_nnc_tensor_t* const gb = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 2, 2), 0); |
61 | 1 | ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(a, indices), TENSOR_LIST(ga, gindices), 0); |
62 | 1 | ccv_nnc_cmd_exec(CMD_INDEX_SELECT_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(ga, gindices), TENSOR_LIST(gb), 0); |
63 | 1 | ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(gb), TENSOR_LIST(b), 0); |
64 | 1 | float btp[] = { |
65 | 1 | 2.5, 3.5, |
66 | 1 | 1.4, 2.4, |
67 | 1 | }; |
68 | 1 | REQUIRE_ARRAY_EQ_WITH_TOLERANCE(float, b->data.f32, btp, 4, 1e-5, "should be equal"); |
69 | 1 | ccv_nnc_tensor_free(a); |
70 | 1 | ccv_nnc_tensor_free(indices); |
71 | 1 | ccv_nnc_tensor_free(b); |
72 | 1 | ccv_nnc_tensor_free(ga); |
73 | 1 | ccv_nnc_tensor_free(gindices); |
74 | 1 | ccv_nnc_tensor_free(gb); |
75 | 1 | } |
76 | | |
77 | | TEST_CASE("index select a 1d tensor") |
78 | 1 | { |
79 | 1 | GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_INDEX_SELECT_FORWARD, CCV_NNC_BACKEND_GPU_REF) || ccv_nnc_cmd_ok(CCV_NNC_INDEX_SELECT_FORWARD, CCV_NNC_BACKEND_MPS)); |
80 | 1 | float ap[] = { |
81 | 1 | 1, 2, 3, 4, 5 |
82 | 1 | }; |
83 | 1 | ccv_nnc_tensor_t* const a = ccv_nnc_tensor_new(ap, CPU_TENSOR_NHWC(32F, 5), 0); |
84 | 1 | int ip[] = {3, 2, 4}; |
85 | 1 | ccv_nnc_tensor_t* const indices = ccv_nnc_tensor_new(ip, CPU_TENSOR_NHWC(32S, 3), 0); |
86 | 1 | ccv_nnc_tensor_t* const b = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 3), 0); |
87 | 1 | ccv_nnc_tensor_t* const ga = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 5), 0); |
88 | 1 | ccv_nnc_tensor_t* const gindices = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32S, 3), 0); |
89 | 1 | ccv_nnc_tensor_t* const gb = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 3), 0); |
90 | 1 | ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(a, indices), TENSOR_LIST(ga, gindices), 0); |
91 | 1 | ccv_nnc_cmd_exec(CMD_INDEX_SELECT_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(ga, gindices), TENSOR_LIST(gb), 0); |
92 | 1 | ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(gb), TENSOR_LIST(b), 0); |
93 | 1 | float btp[] = { |
94 | 1 | 4, 3, 5 |
95 | 1 | }; |
96 | 1 | ccv_nnc_tensor_t const bt = ccv_nnc_tensor(btp, CPU_TENSOR_NHWC(32F, 3), 0); |
97 | 1 | REQUIRE_TENSOR_EQ(b, &bt, "should be equal"); |
98 | 1 | ccv_nnc_tensor_free(a); |
99 | 1 | ccv_nnc_tensor_free(indices); |
100 | 1 | ccv_nnc_tensor_free(b); |
101 | 1 | ccv_nnc_tensor_free(ga); |
102 | 1 | ccv_nnc_tensor_free(gindices); |
103 | 1 | ccv_nnc_tensor_free(gb); |
104 | 1 | } |
105 | | |
106 | | TEST_CASE("index select a tensor view") |
107 | | { |
108 | | GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_INDEX_SELECT_FORWARD, CCV_NNC_BACKEND_GPU_REF) || ccv_nnc_cmd_ok(CCV_NNC_INDEX_SELECT_FORWARD, CCV_NNC_BACKEND_MPS)); |
109 | | float ap[] = { |
110 | | 1, 2, 3, 4, |
111 | | 2, 3, 4, 5, |
112 | | 3, 4, 5, 6, |
113 | | }; |
114 | | ccv_nnc_tensor_t* const a = ccv_nnc_tensor_new(ap, CPU_TENSOR_NHWC(32F, 3, 4), 0); |
115 | | ccv_nnc_tensor_view_t* const av = ccv_nnc_tensor_view_new(a, CPU_TENSOR_NHWC(32F, 3, 2), DIM_ALLOC(0, 1), DIM_ALLOC(4, 1)); |
116 | | int ip[] = {1, 1}; |
117 | | ccv_nnc_tensor_t* const indices = ccv_nnc_tensor_new(ip, CPU_TENSOR_NHWC(32S, 2), 0); |
118 | | ccv_nnc_tensor_t* const b = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 2, 4), 0); |
119 | | memset(b->data.f32, 0, 2 * 4 * sizeof(float)); |
120 | | ccv_nnc_tensor_view_t* const bv = ccv_nnc_tensor_view_new(b, CPU_TENSOR_NHWC(32F, 2, 2), DIM_ALLOC(0, 1), DIM_ALLOC(4, 1)); |
121 | | ccv_nnc_tensor_t* const ga = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 3, 4), 0); |
122 | | ccv_nnc_tensor_view_t* const gav = ccv_nnc_tensor_view_new(ga, GPU_TENSOR_NHWC(000, 32F, 3, 2), DIM_ALLOC(0, 1), DIM_ALLOC(4, 1)); |
123 | | ccv_nnc_tensor_t* const gindices = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32S, 2), 0); |
124 | | ccv_nnc_tensor_t* const gb = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 2, 4), 0); |
125 | | ccv_nnc_tensor_view_t* const gbv = ccv_nnc_tensor_view_new(gb, GPU_TENSOR_NHWC(000, 32F, 2, 2), DIM_ALLOC(0, 1), DIM_ALLOC(4, 1)); |
126 | | ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(a, indices, b), TENSOR_LIST(ga, gindices, gb), 0); |
127 | | ccv_nnc_cmd_exec(CMD_INDEX_SELECT_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST((ccv_nnc_tensor_t*)gav, gindices), TENSOR_LIST((ccv_nnc_tensor_t*)gbv), 0); |
128 | | ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(gb), TENSOR_LIST(b), 0); |
129 | | float btp[] = { |
130 | | 0, 3, 4, 0, |
131 | | 0, 3, 4, 0, |
132 | | }; |
133 | | ccv_nnc_tensor_t const bt = ccv_nnc_tensor(btp, CPU_TENSOR_NHWC(32F, 2, 4), 0); |
134 | | REQUIRE_TENSOR_EQ(b, &bt, "should be equal"); |
135 | | ccv_nnc_tensor_free(a); |
136 | | ccv_nnc_tensor_view_free(av); |
137 | | ccv_nnc_tensor_free(indices); |
138 | | ccv_nnc_tensor_free(b); |
139 | | ccv_nnc_tensor_view_free(bv); |
140 | | ccv_nnc_tensor_free(ga); |
141 | | ccv_nnc_tensor_view_free(gav); |
142 | | ccv_nnc_tensor_free(gindices); |
143 | | ccv_nnc_tensor_free(gb); |
144 | | ccv_nnc_tensor_view_free(gbv); |
145 | | } |
146 | | |
147 | | TEST_CASE("backward index select a tensor") |
148 | 1 | { |
149 | 1 | GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_INDEX_SELECT_BACKWARD, CCV_NNC_BACKEND_GPU_REF)); |
150 | 1 | float bp[] = { |
151 | 1 | 1, 2, |
152 | 1 | 2, 3, |
153 | 1 | }; |
154 | 1 | ccv_nnc_tensor_t* const a = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 3, 2), 0); |
155 | 1 | int ip[] = {1, 1}; |
156 | 1 | ccv_nnc_tensor_t* const indices = ccv_nnc_tensor_new(ip, CPU_TENSOR_NHWC(32S, 2), 0); |
157 | 1 | ccv_nnc_tensor_t* const b = ccv_nnc_tensor_new(bp, CPU_TENSOR_NHWC(32F, 2, 2), 0); |
158 | 1 | ccv_nnc_tensor_t* const ga = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 3, 2), 0); |
159 | 1 | ccv_nnc_tensor_t* const gindices = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32S, 2), 0); |
160 | 1 | ccv_nnc_tensor_t* const gb = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 2, 2), 0); |
161 | 1 | ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(b, indices), TENSOR_LIST(gb, gindices), 0); |
162 | 1 | ccv_nnc_cmd_exec(CMD_INDEX_SELECT_BACKWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(gb, 0, gindices), TENSOR_LIST(ga), 0); |
163 | 1 | ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(ga), TENSOR_LIST(a), 0); |
164 | 1 | float atp[] = { |
165 | 1 | 0, 0, |
166 | 1 | 3, 5, |
167 | 1 | 0, 0, |
168 | 1 | }; |
169 | 1 | ccv_nnc_tensor_t const at = ccv_nnc_tensor(atp, CPU_TENSOR_NHWC(32F, 3, 2), 0); |
170 | 1 | REQUIRE_TENSOR_EQ(a, &at, "should be equal"); |
171 | 1 | ccv_nnc_tensor_free(a); |
172 | 1 | ccv_nnc_tensor_free(indices); |
173 | 1 | ccv_nnc_tensor_free(b); |
174 | 1 | ccv_nnc_tensor_free(ga); |
175 | 1 | ccv_nnc_tensor_free(gindices); |
176 | 1 | ccv_nnc_tensor_free(gb); |
177 | 1 | } |
178 | | |
179 | | TEST_CASE("backward index select a 1d tensor") |
180 | 1 | { |
181 | 1 | GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_INDEX_SELECT_BACKWARD, CCV_NNC_BACKEND_GPU_REF)); |
182 | 1 | float bp[] = { |
183 | 1 | 4, 3, 5, |
184 | 1 | }; |
185 | 1 | ccv_nnc_tensor_t* const a = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 5), 0); |
186 | 1 | int ip[] = {3, 2, 4}; |
187 | 1 | ccv_nnc_tensor_t* const indices = ccv_nnc_tensor_new(ip, CPU_TENSOR_NHWC(32S, 3), 0); |
188 | 1 | ccv_nnc_tensor_t* const b = ccv_nnc_tensor_new(bp, CPU_TENSOR_NHWC(32F, 3), 0); |
189 | 1 | ccv_nnc_tensor_t* const ga = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 5), 0); |
190 | 1 | ccv_nnc_tensor_t* const gindices = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32S, 3), 0); |
191 | 1 | ccv_nnc_tensor_t* const gb = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 3), 0); |
192 | 1 | ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(b, indices), TENSOR_LIST(gb, gindices), 0); |
193 | 1 | ccv_nnc_cmd_exec(CMD_INDEX_SELECT_BACKWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(gb, 0, gindices), TENSOR_LIST(ga), 0); |
194 | 1 | ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(ga), TENSOR_LIST(a), 0); |
195 | 1 | float atp[] = { |
196 | 1 | 0, 0, 3, 4, 5 |
197 | 1 | }; |
198 | 1 | ccv_nnc_tensor_t const at = ccv_nnc_tensor(atp, CPU_TENSOR_NHWC(32F, 5), 0); |
199 | 1 | REQUIRE_TENSOR_EQ(a, &at, "should be equal"); |
200 | 1 | ccv_nnc_tensor_free(a); |
201 | 1 | ccv_nnc_tensor_free(indices); |
202 | 1 | ccv_nnc_tensor_free(b); |
203 | 1 | ccv_nnc_tensor_free(ga); |
204 | 1 | ccv_nnc_tensor_free(gindices); |
205 | 1 | ccv_nnc_tensor_free(gb); |
206 | 1 | } |
207 | | |
208 | | TEST_CASE("backward index select a tensor view") |
209 | 1 | { |
210 | 1 | GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_INDEX_SELECT_BACKWARD, CCV_NNC_BACKEND_GPU_REF)); |
211 | 1 | float bp[] = { |
212 | 1 | 0, 3, 4, 0, |
213 | 1 | 0, 1, 5, 0, |
214 | 1 | }; |
215 | 1 | ccv_nnc_tensor_t* const a = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 3, 4), 0); |
216 | 1 | int i; |
217 | 13 | for (i = 0; i < 3 * 4; i++12 ) |
218 | 12 | a->data.f32[i] = i; |
219 | 1 | ccv_nnc_tensor_view_t* const av = ccv_nnc_tensor_view_new(a, CPU_TENSOR_NHWC(32F, 3, 2), DIM_ALLOC(0, 1), DIM_ALLOC(4, 1)); |
220 | 1 | int ip[] = {1, 1}; |
221 | 1 | ccv_nnc_tensor_t* const indices = ccv_nnc_tensor_new(ip, CPU_TENSOR_NHWC(32S, 2), 0); |
222 | 1 | ccv_nnc_tensor_t* const b = ccv_nnc_tensor_new(bp, CPU_TENSOR_NHWC(32F, 2, 4), 0); |
223 | 1 | ccv_nnc_tensor_view_t* const bv = ccv_nnc_tensor_view_new(b, CPU_TENSOR_NHWC(32F, 2, 2), DIM_ALLOC(0, 1), DIM_ALLOC(4, 1)); |
224 | 1 | ccv_nnc_tensor_t* const ga = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 3, 4), 0); |
225 | 1 | ccv_nnc_tensor_view_t* const gav = ccv_nnc_tensor_view_new(ga, GPU_TENSOR_NHWC(000, 32F, 3, 2), DIM_ALLOC(0, 1), DIM_ALLOC(4, 1)); |
226 | 1 | ccv_nnc_tensor_t* const gindices = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32S, 2), 0); |
227 | 1 | ccv_nnc_tensor_t* const gb = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, 2, 4), 0); |
228 | 1 | ccv_nnc_tensor_view_t* const gbv = ccv_nnc_tensor_view_new(gb, GPU_TENSOR_NHWC(000, 32F, 2, 2), DIM_ALLOC(0, 1), DIM_ALLOC(4, 1)); |
229 | 1 | ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(a, indices, b), TENSOR_LIST(ga, gindices, gb), 0); |
230 | 1 | ccv_nnc_cmd_exec(CMD_INDEX_SELECT_BACKWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST((ccv_nnc_tensor_t*)gbv, 0, gindices), TENSOR_LIST((ccv_nnc_tensor_t*)gav), 0); |
231 | 1 | ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(ga), TENSOR_LIST(a), 0); |
232 | 1 | float atp[] = { |
233 | 1 | 0, 0, 0, 3, |
234 | 1 | 4, 4, 9, 7, |
235 | 1 | 8, 0, 0, 11, |
236 | 1 | }; |
237 | 1 | ccv_nnc_tensor_t const at = ccv_nnc_tensor(atp, CPU_TENSOR_NHWC(32F, 3, 4), 0); |
238 | 1 | REQUIRE_TENSOR_EQ(a, &at, "should be equal"); |
239 | 1 | ccv_nnc_tensor_free(a); |
240 | 1 | ccv_nnc_tensor_view_free(av); |
241 | 1 | ccv_nnc_tensor_free(indices); |
242 | 1 | ccv_nnc_tensor_free(b); |
243 | 1 | ccv_nnc_tensor_view_free(bv); |
244 | 1 | ccv_nnc_tensor_free(ga); |
245 | 1 | ccv_nnc_tensor_view_free(gav); |
246 | 1 | ccv_nnc_tensor_free(gindices); |
247 | 1 | ccv_nnc_tensor_free(gb); |
248 | 1 | ccv_nnc_tensor_view_free(gbv); |
249 | 1 | } |
250 | | |
251 | | TEST_CASE("index select forward with half precision") |
252 | 1 | { |
253 | 1 | GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_INDEX_SELECT_FORWARD, CCV_NNC_BACKEND_GPU_REF) || ccv_nnc_cmd_ok(CCV_NNC_INDEX_SELECT_FORWARD, CCV_NNC_BACKEND_MPS)); |
254 | 1 | dsfmt_t dsfmt; |
255 | 1 | dsfmt_init_gen_rand(&dsfmt, 0); |
256 | 1 | ccv_nnc_tensor_t* const a = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 100, 10), 0); |
257 | 1 | int i; |
258 | 1.00k | for (i = 0; i < 100 * 10; i++1.00k ) |
259 | 1.00k | a->data.f32[i] = dsfmt_genrand_open_close(&dsfmt); |
260 | 1 | ccv_nnc_tensor_t* const a16 = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(16F, 100, 10), 0); |
261 | 1 | ccv_nnc_cmd_exec(CMD_DATATYPE_CONVERSION_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(a), TENSOR_LIST(a16), 0); |
262 | 1 | ccv_nnc_tensor_t* const indices = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32S, 10), 0); |
263 | 11 | for (i = 0; i < 10; i++10 ) |
264 | 10 | indices->data.i32[i] = i * 9 + 1; |
265 | 1 | ccv_nnc_tensor_t* const b = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(16F, 10, 10), 0); |
266 | 1 | ccv_nnc_tensor_t* const ga = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 16F, 100, 10), 0); |
267 | 1 | ccv_nnc_tensor_t* const gindices = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32S, 10), 0); |
268 | 1 | ccv_nnc_tensor_t* const gb = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 16F, 10, 10), 0); |
269 | 1 | ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(a16, indices), TENSOR_LIST(ga, gindices), 0); |
270 | 1 | ccv_nnc_cmd_exec(CMD_INDEX_SELECT_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(ga, gindices), TENSOR_LIST(gb), 0); |
271 | 1 | ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(gb), TENSOR_LIST(b), 0); |
272 | 1 | ccv_nnc_tensor_t* const bt = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(16F, 10, 10), 0); |
273 | 1 | ccv_nnc_cmd_exec(CMD_INDEX_SELECT_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(a16, indices), TENSOR_LIST(bt), 0); |
274 | 1 | ccv_nnc_tensor_t* const b32 = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 10, 10), 0); |
275 | 1 | ccv_nnc_tensor_t* const bt32 = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 10, 10), 0); |
276 | 1 | ccv_nnc_cmd_exec(CMD_DATATYPE_CONVERSION_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(b, bt), TENSOR_LIST(b32, bt32), 0); |
277 | 1 | REQUIRE_TENSOR_EQ(b32, bt32, "should be equal"); |
278 | 1 | ccv_nnc_tensor_free(a); |
279 | 1 | ccv_nnc_tensor_free(indices); |
280 | 1 | ccv_nnc_tensor_free(b); |
281 | 1 | ccv_nnc_tensor_free(ga); |
282 | 1 | ccv_nnc_tensor_free(gindices); |
283 | 1 | ccv_nnc_tensor_free(gb); |
284 | 1 | ccv_nnc_tensor_free(a16); |
285 | 1 | ccv_nnc_tensor_free(bt); |
286 | 1 | ccv_nnc_tensor_free(b32); |
287 | 1 | ccv_nnc_tensor_free(bt32); |
288 | 1 | } |
289 | | |
290 | | TEST_CASE("index select backward with half precision") |
291 | 1 | { |
292 | 1 | GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_INDEX_SELECT_BACKWARD, CCV_NNC_BACKEND_GPU_REF)); |
293 | 1 | dsfmt_t dsfmt; |
294 | 1 | dsfmt_init_gen_rand(&dsfmt, 0); |
295 | 1 | ccv_nnc_tensor_t* const a = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 10, 10), 0); |
296 | 1 | int i; |
297 | 101 | for (i = 0; i < 10 * 10; i++100 ) |
298 | 100 | a->data.f32[i] = dsfmt_genrand_open_close(&dsfmt); |
299 | 1 | ccv_nnc_tensor_t* const a16 = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(16F, 10, 10), 0); |
300 | 1 | ccv_nnc_cmd_exec(CMD_DATATYPE_CONVERSION_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(a), TENSOR_LIST(a16), 0); |
301 | 1 | ccv_nnc_tensor_t* const indices = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32S, 10), 0); |
302 | 11 | for (i = 0; i < 10; i++10 ) |
303 | 10 | indices->data.i32[i] = i * 9 + 1; |
304 | 1 | ccv_nnc_tensor_t* const b = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(16F, 100, 10), 0); |
305 | 1 | ccv_nnc_tensor_t* const ga = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 16F, 10, 10), 0); |
306 | 1 | ccv_nnc_tensor_t* const gindices = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32S, 10), 0); |
307 | 1 | ccv_nnc_tensor_t* const gb = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 16F, 100, 10), 0); |
308 | 1 | ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(a16, indices), TENSOR_LIST(ga, gindices), 0); |
309 | 1 | ccv_nnc_cmd_exec(CMD_INDEX_SELECT_BACKWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(ga, 0, gindices), TENSOR_LIST(gb), 0); |
310 | 1 | ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(gb), TENSOR_LIST(b), 0); |
311 | 1 | ccv_nnc_tensor_t* const bt = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(16F, 100, 10), 0); |
312 | 1 | ccv_nnc_cmd_exec(CMD_INDEX_SELECT_BACKWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(a16, 0, indices), TENSOR_LIST(bt), 0); |
313 | 1 | ccv_nnc_tensor_t* const b32 = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 100, 10), 0); |
314 | 1 | ccv_nnc_tensor_t* const bt32 = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, 100, 10), 0); |
315 | 1 | ccv_nnc_cmd_exec(CMD_DATATYPE_CONVERSION_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(b, bt), TENSOR_LIST(b32, bt32), 0); |
316 | 1 | REQUIRE_TENSOR_EQ(b32, bt32, "should be equal"); |
317 | 1 | ccv_nnc_tensor_free(a); |
318 | 1 | ccv_nnc_tensor_free(indices); |
319 | 1 | ccv_nnc_tensor_free(b); |
320 | 1 | ccv_nnc_tensor_free(ga); |
321 | 1 | ccv_nnc_tensor_free(gindices); |
322 | 1 | ccv_nnc_tensor_free(gb); |
323 | 1 | ccv_nnc_tensor_free(a16); |
324 | 1 | ccv_nnc_tensor_free(bt); |
325 | 1 | ccv_nnc_tensor_free(b32); |
326 | 1 | ccv_nnc_tensor_free(bt32); |
327 | 1 | } |
328 | | |
329 | | #include "case_main.h" |