Coverage Report

Created: 2025-05-25 22:01

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/home/liu/actions-runner/_work/ccv/ccv/lib/nnc/cmd/unique_consecutive/ccv_nnc_unique_consecutive.c
Line
Count
Source
1
#include "ccv.h"
2
#include "nnc/ccv_nnc.h"
3
#include "nnc/ccv_nnc_internal.h"
4
5
static int _ccv_nnc_unique_consecutive_forw_bitmask(const ccv_nnc_cmd_param_t cmd, const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
6
4
{
7
4
  if ((input_bitmasks[0] & 1u) == 1u && output_bitmasks[0] == 3u)
8
4
    return 1;
9
0
  return 0;
10
4
}
11
12
static int _ccv_nnc_unique_consecutive_back_bitmask(const ccv_nnc_cmd_param_t cmd, const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
13
0
{
14
  // 10001
15
0
  if ((input_bitmasks[0] & 17u) == 17u && (output_bitmasks[0] & 1u) == 1u)
16
0
    return 1;
17
0
  return 0;
18
0
}
19
20
static void _ccv_nnc_unique_consecutive_tensor_auto_forw(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* const inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* const outputs, const int output_size)
21
3
{
22
3
  assert(input_size >= 1);
23
3
  assert(output_size == 2);
24
3
  outputs[0] = inputs[0];
25
3
  if (cmd.unique_consecutive.bincount > 0)
26
3
    outputs[0].dim[0] = ccv_min(outputs[0].dim[0], cmd.unique_consecutive.bincount);
27
3
  outputs[1] = outputs[0];
28
3
  outputs[1].datatype = CCV_32S;
29
3
}
30
31
REGISTER_COMMAND(CCV_NNC_UNIQUE_CONSECUTIVE_FORWARD)(ccv_nnc_cmd_registry_t* const registry)
32
  FIND_BACKEND(ccv_nnc_unique_consecutive_cpu_ref.c, gpu/ccv_nnc_unique_consecutive_gpu_ref.cu, mps/ccv_nnc_unique_consecutive_mps.m)
33
1
{
34
1
  registry->bitmask = _ccv_nnc_unique_consecutive_forw_bitmask;
35
1
  registry->tensor_auto = _ccv_nnc_unique_consecutive_tensor_auto_forw;
36
1
}
37
38
REGISTER_COMMAND(CCV_NNC_UNIQUE_CONSECUTIVE_BACKWARD)(ccv_nnc_cmd_registry_t* const registry)
39
  FIND_BACKEND(ccv_nnc_unique_consecutive_cpu_ref.c, gpu/ccv_nnc_unique_consecutive_gpu_ref.cu, mps/ccv_nnc_unique_consecutive_mps.m)
40
1
{
41
1
  registry->bitmask = _ccv_nnc_unique_consecutive_back_bitmask;
42
1
  registry->tensor_auto = ccv_nnc_hint_tensor_auto_backward_from_gradient; // This is just best guess.
43
1
}
44
45
//@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_UNIQUE_CONSECUTIVE_FORWARD)
46
#define CMD_UNIQUE_CONSECUTIVE_FORWARD(_bincount) ccv_nnc_cmd(CCV_NNC_UNIQUE_CONSECUTIVE_FORWARD, 0, ((ccv_nnc_cmd_param_t){.size={.dim={1,1,1}},.unique_consecutive={.bincount=_bincount}}), 0)
47
//@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_UNIQUE_CONSECUTIVE_BACKWARD)
48
#define CMD_UNIQUE_CONSECUTIVE_BACKWARD(_bincount) ccv_nnc_cmd(CCV_NNC_UNIQUE_CONSECUTIVE_BACKWARD, 0, ((ccv_nnc_cmd_param_t){.size={.dim={1,1,1}},.unique_consecutive={.bincount=_bincount}}), 0)