## Coverage Report

#### Created: 2026-04-14 11:10

next uncovered line (L), next uncovered region (R), next uncovered branch (B)

    /home/liu/actions-runner/_work/ccv/ccv/lib/nnc/cmd/tanh/ccv_nnc_tanh.c

    Line
    Count
    Source
    1
    #include "ccv.h"
    2
    #include "nnc/ccv_nnc.h"
    3
    #include "nnc/ccv_nnc_easy.h"
    4
    #include "nnc/ccv_nnc_internal.h"
    5
    6
    static int _ccv_nnc_tanh_allow_first_replace(const ccv_nnc_cmd_param_t cmd, const int input_idx, const int input_size, const int output_idx, const int output_size)
    7
    9
    {
    8
    9
      return input_idx == 0 && output_idx == 06;
    9
    9
    }
    10
    11
    static int _ccv_nnc_tanh_forw_bitmask(const ccv_nnc_cmd_param_t cmd, const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
    12
    0
    {
    13
    0
      if ((input_bitmasks[0] & 1u) == 1u && output_bitmasks[0] == 1u)
    14
    0
        return 1;
    15
    0
      return 0;
    16
    0
    }
    17
    18
    static int _ccv_nnc_tanh_back_bitmask(const ccv_nnc_cmd_param_t cmd, const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
    19
    14
    {
    20
      // gradient, [x], y
    21
    14
      if ((input_bitmasks[0] & 5u) == 5u && (output_bitmasks[0] & 1u) == 1u6)
    22
    6
        return 1;
    23
    8
      return 0;
    24
    14
    }
    25
    26
    static void _ccv_nnc_tanh_tensor_auto_forw(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* const inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* const outputs, const int output_size)
    27
    8
    {
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    8
      assert(input_size == 1);
    29
    8
      assert(output_size == 1);
    30
    8
      outputs[0] = inputs[0];
    31
    8
    }
    32
    33
    static void _ccv_nnc_tanh_tensor_auto_back(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* const inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* const outputs, const int output_size)
    34
    3
    {
    35
    3
      assert(input_size >= 3);
    36
    3
      assert(output_size >= 1);
    37
    3
      outputs[0] = inputs[2];
    38
    3
    }
    39
    40
    REGISTER_COMMAND(CCV_NNC_TANH_FORWARD)(ccv_nnc_cmd_registry_t* const registry)
    41
      FIND_BACKEND(ccv_nnc_tanh_cpu_ref.c, gpu/ccv_nnc_tanh_gpu_cudnn.cu, mps/ccv_nnc_tanh_mps.m)
    42
    1
    {
    43
    1
      registry->bitmask = _ccv_nnc_tanh_forw_bitmask;
    44
    1
      registry->allow_inplace = _ccv_nnc_tanh_allow_first_replace;
    45
    1
      registry->tensor_auto = _ccv_nnc_tanh_tensor_auto_forw;
    46
    1
    }
    47
    48
    REGISTER_COMMAND(CCV_NNC_TANH_BACKWARD)(ccv_nnc_cmd_registry_t* const registry)
    49
      FIND_BACKEND(ccv_nnc_tanh_cpu_ref.c, gpu/ccv_nnc_tanh_gpu_cudnn.cu, mps/ccv_nnc_tanh_mps.m)
    50
    1
    {
    51
    1
      registry->flags = CCV_NNC_CMD_ATTR_NULL_IS_ONES;
    52
    1
      registry->bitmask = _ccv_nnc_tanh_back_bitmask;
    53
    1
      registry->allow_inplace = _ccv_nnc_tanh_allow_first_replace;
    54
    1
      registry->tensor_auto = _ccv_nnc_tanh_tensor_auto_back;
    55
    1
    }
    56
    57
    //@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_TANH_FORWARD)
    58
    #define CMD_TANH_FORWARD() ccv_nnc_cmd(CCV_NNC_TANH_FORWARD, 0, ccv_nnc_cmd_auto, 0)
    59
    //@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_TANH_BACKWARD)
    60
    #define CMD_TANH_BACKWARD() ccv_nnc_cmd(CCV_NNC_TANH_BACKWARD, 0, ccv_nnc_cmd_auto, 0)