## Coverage Report

#### Created: 2026-04-14 19:22

next uncovered line (L), next uncovered region (R), next uncovered branch (B)

    /home/liu/actions-runner/_work/ccv/ccv/lib/nnc/cmd/index/ccv_nnc_index_select.c

    Line
    Count
    Source
    1
    #include "ccv.h"
    2
    #include "nnc/ccv_nnc.h"
    3
    #include "nnc/ccv_nnc_internal.h"
    4
    5
    static int _ccv_nnc_index_select_forw_bitmask(const ccv_nnc_cmd_param_t cmd, const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
    6
    6
    {
    7
    6
      if ((input_bitmasks[0] & 3u) == 3u && output_bitmasks[0] == 1u)
    8
    6
        return 1;
    9
    0
      return 0;
    10
    6
    }
    11
    12
    static int _ccv_nnc_index_select_back_bitmask(const ccv_nnc_cmd_param_t cmd, const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
    13
    152
    {
    14
    152
      if ((input_bitmasks[0] & 5u) == 5u && (output_bitmasks[0] & 1u) == 1u76)
    15
    76
        return 1;
    16
    76
      return 0;
    17
    152
    }
    18
    19
    static void _ccv_nnc_index_select_tensor_auto_forw(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* const inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* const outputs, const int output_size)
    20
    37
    {
    21
    37
      assert(input_size >= 2);
    22
    37
      assert(output_size == 1);
    23
    37
      outputs[0] = inputs[0];
    24
    37
      outputs[0].dim[0] = inputs[1].dim[0];
    25
    37
    }
    26
    27
    REGISTER_COMMAND(CCV_NNC_INDEX_SELECT_FORWARD)(ccv_nnc_cmd_registry_t* const registry)
    28
      FIND_BACKEND(ccv_nnc_index_select_cpu_ref.c, gpu/ccv_nnc_index_select_gpu_ref.cu, mps/ccv_nnc_index_select_mps.m)
    29
    1
    {
    30
    1
      registry->bitmask = _ccv_nnc_index_select_forw_bitmask;
    31
    1
      registry->tensor_auto = _ccv_nnc_index_select_tensor_auto_forw;
    32
    1
    }
    33
    34
    REGISTER_COMMAND(CCV_NNC_INDEX_SELECT_BACKWARD)(ccv_nnc_cmd_registry_t* const registry)
    35
      FIND_BACKEND(ccv_nnc_index_select_cpu_ref.c, gpu/ccv_nnc_index_select_gpu_ref.cu, mps/ccv_nnc_index_select_mps.m)
    36
    1
    {
    37
    1
      registry->bitmask = _ccv_nnc_index_select_back_bitmask;
    38
    1
      registry->tensor_auto = ccv_nnc_hint_tensor_auto_backward_from_gradient; // This is just best guess.
    39
    1
    }
    40
    41
    //@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_INDEX_SELECT_FORWARD)
    42
    #define CMD_INDEX_SELECT_FORWARD() ccv_nnc_cmd(CCV_NNC_INDEX_SELECT_FORWARD, 0, ccv_nnc_cmd_auto, 0)
    43
    //@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_INDEX_SELECT_BACKWARD)
    44
    #define CMD_INDEX_SELECT_BACKWARD() ccv_nnc_cmd(CCV_NNC_INDEX_SELECT_BACKWARD, 0, ccv_nnc_cmd_auto, 0)