## Coverage Report

#### Created: 2026-04-20 13:39

next uncovered line (L), next uncovered region (R), next uncovered branch (B)

    /home/liu/actions-runner/_work/ccv/ccv/lib/nnc/cmd/blas/ccv_nnc_rotate_half.c

    Line
    Count
    Source
    1
    #include "ccv.h"
    2
    #include "nnc/ccv_nnc.h"
    3
    #include "nnc/ccv_nnc_internal.h"
    4
    #include "nnc/ccv_nnc_easy.h"
    5
    6
    static int _ccv_nnc_rotate_half_allow_first_replace(const ccv_nnc_cmd_param_t cmd, const int input_idx, const int input_size, const int output_idx, const int output_size)
    7
    0
    {
    8
    0
      return 0;
    9
    0
    }
    10
    11
    static int _ccv_nnc_rotate_half_forw_bitmask(const ccv_nnc_cmd_param_t cmd, const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
    12
    0
    {
    13
    0
      if ((input_bitmasks[0] & 1u) == 1u && output_bitmasks[0] == 1u)
    14
    0
        return 1;
    15
    0
      return 0;
    16
    0
    }
    17
    18
    static int _ccv_nnc_rotate_half_back_bitmask(const ccv_nnc_cmd_param_t cmd, const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
    19
    0
    {
    20
    0
      if ((input_bitmasks[0] & 1u) == 1u && output_bitmasks[0] == 1u)
    21
    0
        return 1;
    22
    0
      return 0;
    23
    0
    }
    24
    25
    REGISTER_COMMAND(CCV_NNC_ROTATE_HALF_FORWARD)(ccv_nnc_cmd_registry_t* const registry)
    26
      FIND_BACKEND(ccv_nnc_rotate_half_cpu_ref.c, gpu/ccv_nnc_rotate_half_gpu_ref.cu, mps/ccv_nnc_rotate_half_mps.m)
    27
    1
    {
    28
    1
      registry->bitmask = _ccv_nnc_rotate_half_forw_bitmask;
    29
    1
      registry->tensor_auto = ccv_nnc_hint_tensor_auto_forward_from_inputs;
    30
    1
      registry->allow_inplace = _ccv_nnc_rotate_half_allow_first_replace;
    31
    1
    }
    32
    33
    REGISTER_COMMAND(CCV_NNC_ROTATE_HALF_BACKWARD)(ccv_nnc_cmd_registry_t* const registry)
    34
      FIND_BACKEND(ccv_nnc_rotate_half_cpu_ref.c, gpu/ccv_nnc_rotate_half_gpu_ref.cu, mps/ccv_nnc_rotate_half_mps.m)
    35
    1
    {
    36
    1
      registry->bitmask = _ccv_nnc_rotate_half_back_bitmask;
    37
    1
      registry->tensor_auto = ccv_nnc_hint_tensor_auto_backward_from_gradient;
    38
    1
      registry->allow_inplace = _ccv_nnc_rotate_half_allow_first_replace;
    39
    1
    }
    40
    41
    //@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_ROTATE_HALF_FORWARD)
    42
    #define CMD_ROTATE_HALF_FORWARD() ccv_nnc_cmd(CCV_NNC_ROTATE_HALF_FORWARD, 0, (ccv_nnc_cmd_param_t){.size={.dim={1,1,1}}}, 0)
    43
    //@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_ROTATE_HALF_BACKWARD)
    44
    #define CMD_ROTATE_HALF_BACKWARD() ccv_nnc_cmd(CCV_NNC_ROTATE_HALF_BACKWARD, 0, (ccv_nnc_cmd_param_t){.size={.dim={1,1,1}}}, 0)