## Coverage Report

#### Created: 2026-04-14 19:45

next uncovered line (L), next uncovered region (R), next uncovered branch (B)

    /home/liu/actions-runner/_work/ccv/ccv/lib/nnc/cmd/nms/ccv_nnc_nms.c

    Line
    Count
    Source
    1
    #include "ccv.h"
    2
    #include "nnc/ccv_nnc.h"
    3
    #include "nnc/ccv_nnc_easy.h"
    4
    #include "nnc/ccv_nnc_internal.h"
    5
    6
    static int _ccv_nnc_nms_forw_bitmask(const ccv_nnc_cmd_param_t cmd, const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
    7
    0
    {
    8
    0
      if ((input_bitmasks[0] & 1u) == 1u && output_bitmasks[0] == 3u)
    9
    0
        return 1;
    10
    0
      return 0;
    11
    0
    }
    12
    13
    static int _ccv_nnc_nms_back_bitmask(const ccv_nnc_cmd_param_t cmd, const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
    14
    0
    {
    15
      // gradient of sorted, gradient of sorting index, input, output of sorted, output of sorting index.
    16
    0
      if ((input_bitmasks[0] & 17u) == ((1u << 0) | (0u << 1) | (0u << 2) | (0u << 3) | (1u << 4)) && output_bitmasks[0] == 1u)
    17
    0
        return 1;
    18
    0
      return 0;
    19
    0
    }
    20
    21
    static void _ccv_nnc_nms_tensor_auto_forw(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* outputs, const int output_size)
    22
    0
    {
    23
    0
      assert(output_size == 2);
    24
    0
      outputs[0] = inputs[0];
    25
    0
      const int nd = ccv_nnc_tensor_nd(inputs[0].dim);
    26
    0
      assert(nd >= 1);
    27
    0
      outputs[1] = inputs[0];
    28
    0
      outputs[1].datatype = CCV_32S;
    29
    0
      memset(outputs[1].dim, 0, sizeof(outputs[1].dim));
    30
    0
      outputs[1].dim[0] = inputs[0].dim[0]; // How many to rank (or batch size).
    31
    0
      outputs[1].dim[1] = (nd <= 2) ? 0 : inputs[0].dim[1]; // How many to rank.
    32
    0
    }
    33
    34
    static void _ccv_nnc_nms_tensor_auto_back(const ccv_nnc_cmd_param_t cmd, const ccv_nnc_tensor_param_t* inputs, const int input_size, const ccv_nnc_hint_t hint, ccv_nnc_tensor_param_t* outputs, const int output_size)
    35
    0
    {
    36
    0
      assert(output_size == 1);
    37
    0
      outputs[0] = inputs[2];
    38
    0
    }
    39
    40
    REGISTER_COMMAND(CCV_NNC_NMS_FORWARD)(ccv_nnc_cmd_registry_t* const registry)
    41
      FIND_BACKEND(ccv_nnc_nms_cpu_ref.c, gpu/ccv_nnc_nms_gpu_ref.cu)
    42
    1
    {
    43
    1
      registry->bitmask = _ccv_nnc_nms_forw_bitmask;
    44
    1
      registry->tensor_auto = _ccv_nnc_nms_tensor_auto_forw;
    45
    1
    }
    46
    47
    REGISTER_COMMAND(CCV_NNC_NMS_BACKWARD)(ccv_nnc_cmd_registry_t* const registry)
    48
      FIND_BACKEND(ccv_nnc_nms_cpu_ref.c, gpu/ccv_nnc_nms_gpu_ref.cu)
    49
    1
    {
    50
    1
      registry->bitmask = _ccv_nnc_nms_back_bitmask;
    51
    1
      registry->tensor_auto = _ccv_nnc_nms_tensor_auto_back;
    52
    1
    }
    53
    54
    //@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_NMS_FORWARD)
    55
    #define CMD_NMS_FORWARD(_iou_threshold) ccv_nnc_cmd(CCV_NNC_NMS_FORWARD, 0, ((ccv_nnc_cmd_param_t){.nms={.iou_threshold=_iou_threshold}}), 0)
    56
    //@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_NMS_BACKWARD)
    57
    #define CMD_NMS_BACKWARD(_iou_threshold) ccv_nnc_cmd(CCV_NNC_NMS_BACKWARD, 0, ((ccv_nnc_cmd_param_t){.nms={.iou_threshold=_iou_threshold}}), 0)