## Coverage Report

#### Created: 2026-04-16 18:32

next uncovered line (L), next uncovered region (R), next uncovered branch (B)

    /home/liu/actions-runner/_work/ccv/ccv/lib/nnc/cmd/rand/ccv_nnc_rand.c

    Line
    Count
    Source
    1
    #include "ccv.h"
    2
    #include "nnc/ccv_nnc.h"
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    #include "nnc/ccv_nnc_internal.h"
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    5
    static int _ccv_nnc_random_bitmask(const ccv_nnc_cmd_param_t cmd, const int input_size, const int output_size, const uint64_t* const input_bitmasks, const int input_bitmask_size, const uint64_t* const output_bitmasks, const int output_bitmask_size)
    6
    0
    {
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    0
      if (output_bitmasks[0] == 1u)
    8
    0
        return 1;
    9
    0
      return 0;
    10
    0
    }
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    12
    REGISTER_COMMAND(CCV_NNC_RANDOM_UNIFORM_FORWARD)(ccv_nnc_cmd_registry_t* const registry)
    13
      FIND_BACKEND(ccv_nnc_rand_uniform_cpu_ref.c, gpu/ccv_nnc_rand_uniform_gpu_ref.cu, mps/ccv_nnc_rand_uniform_mps.m)
    14
    1
    {
    15
    1
      registry->bitmask = _ccv_nnc_random_bitmask;
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    1
      registry->tensor_auto = ccv_nnc_hint_tensor_auto_forward_from_inputs;
    17
    1
    }
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    19
    REGISTER_COMMAND(CCV_NNC_RANDOM_UNIFORM_BACKWARD)(ccv_nnc_cmd_registry_t* const registry)
    20
      FIND_BACKEND(ccv_nnc_rand_uniform_cpu_ref.c, gpu/ccv_nnc_rand_uniform_gpu_ref.cu, mps/ccv_nnc_rand_uniform_mps.m)
    21
    1
    {
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    1
      registry->bitmask = _ccv_nnc_random_bitmask;
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    1
      registry->tensor_auto = ccv_nnc_hint_tensor_auto_forward_from_inputs;
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    1
    }
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    //@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_RANDOM_UNIFORM_FORWARD)
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    #define CMD_RANDOM_UNIFORM_FORWARD(_lb, _ub) ccv_nnc_cmd(CCV_NNC_RANDOM_UNIFORM_FORWARD, 0, (ccv_nnc_cmd_param_t){.size={.dim={1,1,1}},.blas={.a={_lb, _ub}}}, 0)
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    //@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_RANDOM_UNIFORM_BACKWARD)
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    #define CMD_RANDOM_UNIFORM_BACKWARD(_lb, _ub) ccv_nnc_cmd(CCV_NNC_RANDOM_UNIFORM_BACKWARD, 0, (ccv_nnc_cmd_param_t){.size={.dim={1,1,1}},.blas={.a={_lb, _ub}}}, 0)
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    31
    REGISTER_COMMAND(CCV_NNC_RANDOM_NORMAL_FORWARD)(ccv_nnc_cmd_registry_t* const registry)
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      FIND_BACKEND(ccv_nnc_rand_normal_cpu_ref.c, gpu/ccv_nnc_rand_normal_gpu_ref.cu, mps/ccv_nnc_rand_normal_mps.m)
    33
    1
    {
    34
    1
      registry->bitmask = _ccv_nnc_random_bitmask;
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    1
      registry->tensor_auto = ccv_nnc_hint_tensor_auto_forward_from_inputs;
    36
    1
    }
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    38
    REGISTER_COMMAND(CCV_NNC_RANDOM_NORMAL_BACKWARD)(ccv_nnc_cmd_registry_t* const registry)
    39
      FIND_BACKEND(ccv_nnc_rand_normal_cpu_ref.c, gpu/ccv_nnc_rand_normal_gpu_ref.cu, mps/ccv_nnc_rand_normal_mps.m)
    40
    1
    {
    41
    1
      registry->bitmask = _ccv_nnc_random_bitmask;
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    1
      registry->tensor_auto = ccv_nnc_hint_tensor_auto_forward_from_inputs;
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    1
    }
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    45
    //@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_RANDOM_NORMAL_FORWARD)
    46
    #define CMD_RANDOM_NORMAL_FORWARD(_std, _mean) ccv_nnc_cmd(CCV_NNC_RANDOM_NORMAL_FORWARD, 0, (ccv_nnc_cmd_param_t){.size={.dim={1,1,1}},.blas={.a={_std, _mean}}}, 0)
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    //@REGISTER_EASY_COMMAND_MACRO(CCV_NNC_RANDOM_NORMAL_BACKWARD)
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    #define CMD_RANDOM_NORMAL_BACKWARD(_std, _mean) ccv_nnc_cmd(CCV_NNC_RANDOM_NORMAL_BACKWARD, 0, (ccv_nnc_cmd_param_t){.size={.dim={1,1,1}},.blas={.a={_std, _mean}}}, 0)