Coverage Report

Created: 2026-04-03 17:51

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/home/liu/actions-runner/_work/ccv/ccv/lib/nnc/cmd/sigmoid/ccv_nnc_sigmoid_cpu_ref.c
Line
Count
Source
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#include "ccv.h"
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#include "ccv_internal.h"
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#include "nnc/ccv_nnc.h"
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#include "nnc/ccv_nnc_easy.h"
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#include "nnc/ccv_nnc_internal.h"
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#ifdef USE_OPENMP
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#include <omp.h>
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#endif
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#ifdef USE_DISPATCH
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#include <dispatch/dispatch.h>
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#endif
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static int _ccv_nnc_sigmoid_forw(const ccv_nnc_cmd_t cmd, const ccv_nnc_hint_t hint, const int flags, ccv_nnc_tensor_t* const* const inputs, const int input_size, ccv_nnc_tensor_t* const* const outputs, const int output_size, ccv_nnc_stream_context_t* const stream_context)
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14
{
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14
  assert(input_size == 1);
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14
  const ccv_nnc_tensor_t* a = inputs[0];
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14
  assert(CCV_IS_TENSOR_CONTIGUOUS(a));
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14
  assert(output_size == 1);
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14
  ccv_nnc_tensor_t* b = outputs[0];
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14
  assert(CCV_IS_TENSOR_CONTIGUOUS(b));
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14
  const int count = ccv_nnc_tensor_count(a->info);
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14
  int i;
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35
  for (i = 0; i < CCV_NNC_MAX_DIM_ALLOC && a->info.dim[i] > 0; 
i++21
)
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21
    { assert(a->info.dim[i] == b->info.dim[i]); }
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14
  float* const ap = a->data.f32;
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14
  float* const bp = b->data.f32;
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2.54k
  for (i = 0; i < count; 
i++2.52k
)
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2.52k
    bp[i] = 1. / (1. + exp(-ap[i]));
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14
  return CCV_NNC_EXEC_SUCCESS;
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14
}
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static int _ccv_nnc_sigmoid_back(const ccv_nnc_cmd_t cmd, const ccv_nnc_hint_t hint, const int flags, ccv_nnc_tensor_t* const* const inputs, const int input_size, ccv_nnc_tensor_t* const* const outputs, const int output_size, ccv_nnc_stream_context_t* const stream_context)
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7
{
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7
  assert(input_size == 3);
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7
  assert(output_size == 1);
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7
  const ccv_nnc_tensor_t* g = inputs[0];
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7
  const ccv_nnc_tensor_t* b = inputs[2];
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7
  assert(CCV_IS_TENSOR_CONTIGUOUS(b));
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7
  ccv_nnc_tensor_t* h = outputs[0];
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7
  assert(CCV_IS_TENSOR_CONTIGUOUS(h));
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7
  const int count = ccv_nnc_tensor_count(b->info);
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7
  int i;
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18
  for (i = 0; i < CCV_NNC_MAX_DIM_ALLOC && g->info.dim[i] > 0; 
i++11
)
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11
    { assert(h->info.dim[i] == b->info.dim[i]); }
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7
  if (g)
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7
  {
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7
    assert(CCV_IS_TENSOR_CONTIGUOUS(g));
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18
    
for (i = 0; 7
i < CCV_NNC_MAX_DIM_ALLOC && g->info.dim[i] > 0; 
i++11
)
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11
      { assert(g->info.dim[i] == h->info.dim[i]); }
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7
    float* const gp = g->data.f32;
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7
    float* const bp = b->data.f32;
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7
    float* const hp = h->data.f32;
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2.12k
    for (i = 0; i < count; 
i++2.11k
)
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2.11k
      hp[i] = gp[i] * bp[i] * (1 - bp[i]);
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7
  } else {
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0
    float* const bp = b->data.f32;
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0
    float* const hp = h->data.f32;
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0
    for (i = 0; i < count; i++)
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0
      hp[i] = bp[i] * (1 - bp[i]);
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0
  }
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7
  return CCV_NNC_EXEC_SUCCESS;
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7
}
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REGISTER_COMMAND_BACKEND(CCV_NNC_SIGMOID_FORWARD, CCV_NNC_BACKEND_CPU_REF)(ccv_nnc_cmd_backend_registry_t* const registry)
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1
{
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1
  registry->tensor_formats = CCV_TENSOR_FORMAT_NHWC | CCV_TENSOR_FORMAT_NCHW;
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1
  registry->tensor_datatypes = CCV_32F;
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1
  registry->tensor_memory = CCV_TENSOR_CPU_MEMORY;
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1
  registry->algorithms = 1;
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1
  registry->exec = _ccv_nnc_sigmoid_forw;
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1
}
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REGISTER_COMMAND_BACKEND(CCV_NNC_SIGMOID_BACKWARD, CCV_NNC_BACKEND_CPU_REF)(ccv_nnc_cmd_backend_registry_t* const registry)
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1
{
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1
  registry->tensor_formats = CCV_TENSOR_FORMAT_NHWC | CCV_TENSOR_FORMAT_NCHW;
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1
  registry->tensor_datatypes = CCV_32F;
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1
  registry->tensor_memory = CCV_TENSOR_CPU_MEMORY;
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1
  registry->algorithms = 1;
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1
  registry->exec = _ccv_nnc_sigmoid_back;
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1
}