Coverage Report

Created: 2026-04-18 18:15

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/home/liu/actions-runner/_work/ccv/ccv/lib/nnc/cmd/sigmoid/ccv_nnc_sigmoid_cpu_ref.c
Line
Count
Source
1
#include "ccv.h"
2
#include "ccv_internal.h"
3
#include "nnc/ccv_nnc.h"
4
#include "nnc/ccv_nnc_easy.h"
5
#include "nnc/ccv_nnc_internal.h"
6
#ifdef USE_OPENMP
7
#include <omp.h>
8
#endif
9
#ifdef USE_DISPATCH
10
#include <dispatch/dispatch.h>
11
#endif
12
13
static int _ccv_nnc_sigmoid_forw(const ccv_nnc_cmd_t cmd, const ccv_nnc_hint_t hint, const int flags, ccv_nnc_tensor_t* const* const inputs, const int input_size, ccv_nnc_tensor_t* const* const outputs, const int output_size, ccv_nnc_stream_context_t* const stream_context)
14
14
{
15
14
  assert(input_size == 1);
16
14
  const ccv_nnc_tensor_t* a = inputs[0];
17
14
  assert(CCV_IS_TENSOR_CONTIGUOUS(a));
18
14
  assert(output_size == 1);
19
14
  ccv_nnc_tensor_t* b = outputs[0];
20
14
  assert(CCV_IS_TENSOR_CONTIGUOUS(b));
21
14
  const int count = ccv_nnc_tensor_count(a->info);
22
14
  int i;
23
35
  for (i = 0; i < CCV_NNC_MAX_DIM_ALLOC && a->info.dim[i] > 0; 
i++21
)
24
21
    { assert(a->info.dim[i] == b->info.dim[i]); }
25
14
  float* const ap = a->data.f32;
26
14
  float* const bp = b->data.f32;
27
2.54k
  for (i = 0; i < count; 
i++2.52k
)
28
2.52k
    bp[i] = 1. / (1. + exp(-ap[i]));
29
14
  return CCV_NNC_EXEC_SUCCESS;
30
14
}
31
32
static int _ccv_nnc_sigmoid_back(const ccv_nnc_cmd_t cmd, const ccv_nnc_hint_t hint, const int flags, ccv_nnc_tensor_t* const* const inputs, const int input_size, ccv_nnc_tensor_t* const* const outputs, const int output_size, ccv_nnc_stream_context_t* const stream_context)
33
7
{
34
7
  assert(input_size == 3);
35
7
  assert(output_size == 1);
36
7
  const ccv_nnc_tensor_t* g = inputs[0];
37
7
  const ccv_nnc_tensor_t* b = inputs[2];
38
7
  assert(CCV_IS_TENSOR_CONTIGUOUS(b));
39
7
  ccv_nnc_tensor_t* h = outputs[0];
40
7
  assert(CCV_IS_TENSOR_CONTIGUOUS(h));
41
7
  const int count = ccv_nnc_tensor_count(b->info);
42
7
  int i;
43
18
  for (i = 0; i < CCV_NNC_MAX_DIM_ALLOC && g->info.dim[i] > 0; 
i++11
)
44
11
    { assert(h->info.dim[i] == b->info.dim[i]); }
45
7
  if (g)
46
7
  {
47
7
    assert(CCV_IS_TENSOR_CONTIGUOUS(g));
48
18
    
for (i = 0; 7
i < CCV_NNC_MAX_DIM_ALLOC && g->info.dim[i] > 0; 
i++11
)
49
11
      { assert(g->info.dim[i] == h->info.dim[i]); }
50
7
    float* const gp = g->data.f32;
51
7
    float* const bp = b->data.f32;
52
7
    float* const hp = h->data.f32;
53
2.12k
    for (i = 0; i < count; 
i++2.11k
)
54
2.11k
      hp[i] = gp[i] * bp[i] * (1 - bp[i]);
55
7
  } else {
56
0
    float* const bp = b->data.f32;
57
0
    float* const hp = h->data.f32;
58
0
    for (i = 0; i < count; i++)
59
0
      hp[i] = bp[i] * (1 - bp[i]);
60
0
  }
61
7
  return CCV_NNC_EXEC_SUCCESS;
62
7
}
63
64
REGISTER_COMMAND_BACKEND(CCV_NNC_SIGMOID_FORWARD, CCV_NNC_BACKEND_CPU_REF)(ccv_nnc_cmd_backend_registry_t* const registry)
65
1
{
66
1
  registry->tensor_formats = CCV_TENSOR_FORMAT_NHWC | CCV_TENSOR_FORMAT_NCHW;
67
1
  registry->tensor_datatypes = CCV_32F;
68
1
  registry->tensor_memory = CCV_TENSOR_CPU_MEMORY;
69
1
  registry->algorithms = 1;
70
1
  registry->exec = _ccv_nnc_sigmoid_forw;
71
1
}
72
73
REGISTER_COMMAND_BACKEND(CCV_NNC_SIGMOID_BACKWARD, CCV_NNC_BACKEND_CPU_REF)(ccv_nnc_cmd_backend_registry_t* const registry)
74
1
{
75
1
  registry->tensor_formats = CCV_TENSOR_FORMAT_NHWC | CCV_TENSOR_FORMAT_NCHW;
76
1
  registry->tensor_datatypes = CCV_32F;
77
1
  registry->tensor_memory = CCV_TENSOR_CPU_MEMORY;
78
1
  registry->algorithms = 1;
79
1
  registry->exec = _ccv_nnc_sigmoid_back;
80
1
}