## Coverage Report

#### Created: 2026-05-04 15:30

next uncovered line (L), next uncovered region (R), next uncovered branch (B)

    /home/liu/actions-runner/_work/ccv/ccv/lib/nnc/cmd/rand/ccv_nnc_rand_uniform_cpu_ref.c

    Line
    Count
    Source
    1
    #include "ccv.h"
    2
    #include "ccv_internal.h"
    3
    #include "nnc/ccv_nnc.h"
    4
    #include "nnc/ccv_nnc_easy.h"
    5
    #include "nnc/ccv_nnc_internal.h"
    6
    #include "3rdparty/dsfmt/dSFMT.h"
    7
    #ifdef USE_OPENMP
    8
    #include <omp.h>
    9
    #endif
    10
    #ifdef USE_DISPATCH
    11
    #include <dispatch/dispatch.h>
    12
    #endif
    13
    14
    static int _ccv_nnc_random_uniform(const ccv_nnc_cmd_t cmd, const ccv_nnc_hint_t hint, const int flags, ccv_nnc_tensor_t* const* const inputs, const int input_size, ccv_nnc_tensor_t* const* const outputs, const int output_size, ccv_nnc_stream_context_t* const stream_context)
    15
    55
    {
    16
    55
      assert(output_size == 1);
    17
    55
      ccv_nnc_tensor_t* const a = outputs[0];
    18
    55
      assert(CCV_IS_TENSOR_CONTIGUOUS(a));
    19
    55
      const int count = ccv_nnc_tensor_count(a->info);
    20
    55
      int i;
    21
    55
      float* const ap = a->data.f32;
    22
    55
      dsfmt_t dsfmt;
    23
    55
      dsfmt_init_gen_rand(&dsfmt, ccv_nnc_stream_context_genrand_uint32(stream_context));
    24
    55
      const float l = cmd.info.blas.a[0];
    25
    55
      const float u = cmd.info.blas.a[1];
    26
    12.2M
      for (i = 0; i < count; i++12.2M)
    27
    12.2M
      {
    28
    12.2M
        const float r = dsfmt_genrand_open_open(&dsfmt);
    29
    12.2M
        ap[i] = r * u + (1 - r) * l;
    30
    12.2M
      }
    31
    55
      return CCV_NNC_EXEC_SUCCESS;
    32
    55
    }
    33
    34
    REGISTER_COMMAND_BACKEND(CCV_NNC_RANDOM_UNIFORM_FORWARD, CCV_NNC_BACKEND_CPU_REF)(ccv_nnc_cmd_backend_registry_t* const registry)
    35
    1
    {
    36
    1
      registry->tensor_formats = CCV_TENSOR_FORMAT_NHWC | CCV_TENSOR_FORMAT_NCHW | CCV_TENSOR_FORMAT_CHWN;
    37
    1
      registry->tensor_datatypes = CCV_32F;
    38
    1
      registry->tensor_memory = CCV_TENSOR_CPU_MEMORY;
    39
    1
      registry->algorithms = 1;
    40
    1
      registry->exec = _ccv_nnc_random_uniform;
    41
    1
    }
    42
    43
    REGISTER_COMMAND_BACKEND(CCV_NNC_RANDOM_UNIFORM_BACKWARD, CCV_NNC_BACKEND_CPU_REF)(ccv_nnc_cmd_backend_registry_t* const registry)
    44
    1
    {
    45
    1
      registry->tensor_formats = CCV_TENSOR_FORMAT_NHWC | CCV_TENSOR_FORMAT_NCHW | CCV_TENSOR_FORMAT_CHWN;
    46
    1
      registry->tensor_datatypes = CCV_32F;
    47
    1
      registry->tensor_memory = CCV_TENSOR_CPU_MEMORY;
    48
    1
      registry->algorithms = 1;
    49
    1
      registry->exec = _ccv_nnc_random_uniform;
    50
    1
    }