## Coverage Report

#### Created: 2026-05-04 15:30

next uncovered line (L), next uncovered region (R), next uncovered branch (B)

    /home/liu/actions-runner/_work/ccv/ccv/lib/nnc/cmd/comm/ccv_nnc_comm_cpu_ref.c

    Line
    Count
    Source
    1
    #include "ccv.h"
    2
    #include "ccv_internal.h"
    3
    #include "nnc/ccv_nnc.h"
    4
    #include "nnc/ccv_nnc_easy.h"
    5
    #include "nnc/ccv_nnc_internal.h"
    6
    7
    static int _ccv_nnc_all_to_all_forw_cpu_ref(const ccv_nnc_cmd_t cmd, const ccv_nnc_hint_t hint, const int flags, ccv_nnc_tensor_t* const* const inputs, const int input_size, ccv_nnc_tensor_t* const* const outputs, const int output_size, ccv_nnc_stream_context_t* const stream_context)
    8
    2
    {
    9
    2
      assert(input_size == output_size);
    10
    2
      assert(input_size > 0);
    11
    2
      const int rank_count = input_size;
    12
    2
      assert(CCV_IS_TENSOR_CONTIGUOUS(inputs[0]));
    13
    2
      const int tensor_nd = ccv_nnc_tensor_nd(inputs[0]->info.dim);
    14
    2
      const int axis = cmd.info.all_to_all.axis;
    15
    2
      assert(axis >= 0 && axis < tensor_nd);
    16
    2
      assert(inputs[0]->info.dim[axis] % rank_count == 0);
    17
    2
      const size_t datatype_size = CCV_GET_DATA_TYPE_SIZE(inputs[0]->info.datatype);
    18
    2
      int i, j;
    19
    2
      size_t k;
    20
    2
      size_t inner_count = 1;
    21
    3
      for (i = axis + 1; i < tensor_nd; i++1)
    22
    1
        inner_count *= inputs[0]->info.dim[i];
    23
    2
      size_t outer_count = 1;
    24
    3
      for (i = 0; i < axis; i++1)
    25
    1
        outer_count *= inputs[0]->info.dim[i];
    26
    2
      const size_t axis_dim_count = inputs[0]->info.dim[axis] * inner_count;
    27
    2
      const size_t chunk_count = inputs[0]->info.dim[axis] / rank_count * inner_count;
    28
    2
      const size_t chunk_size = chunk_count * datatype_size;
    29
    10
      for (i = 0; i < rank_count; i++8)
    30
    8
      {
    31
    8
        assert(CCV_IS_TENSOR_CONTIGUOUS(inputs[i]));
    32
    8
        assert(CCV_IS_TENSOR_CONTIGUOUS(outputs[i]));
    33
    8
        assert(inputs[i]->info.format == inputs[0]->info.format);
    34
    8
        assert(outputs[i]->info.format == inputs[0]->info.format);
    35
    8
        assert(inputs[i]->info.datatype == inputs[0]->info.datatype);
    36
    8
        assert(outputs[i]->info.datatype == inputs[0]->info.datatype);
    37
    8
        assert(memcmp(inputs[i]->info.dim, inputs[0]->info.dim, sizeof(inputs[0]->info.dim)) == 0);
    38
    8
        assert(memcmp(outputs[i]->info.dim, inputs[0]->info.dim, sizeof(inputs[0]->info.dim)) == 0);
    39
    8
      }
    40
    10
      for (i = 0; 2i < rank_count; i++8)
    41
    40
        for (j = 0; 8j < rank_count; j++32)
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    32
          assert8(inputs[i] != outputs[j]);
    43
    10
      for (i = 0; 2i < rank_count; i++8)
    44
    40
        for (j = 0; 8j < rank_count; j++32)
    45
    96
          for (k = 0; 32k < outer_count; k++64)
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    64
            memcpy(outputs[j]->data.u8 + (k * axis_dim_count + i * chunk_count) * datatype_size, inputs[i]->data.u8 + (k * axis_dim_count + j * chunk_count) * datatype_size, chunk_size);
    47
    2
      return CCV_NNC_EXEC_SUCCESS;
    48
    2
    }
    49
    50
    static int _ccv_nnc_all_to_all_back_cpu_ref(const ccv_nnc_cmd_t cmd, const ccv_nnc_hint_t hint, const int flags, ccv_nnc_tensor_t* const* const inputs, const int input_size, ccv_nnc_tensor_t* const* const outputs, const int output_size, ccv_nnc_stream_context_t* const stream_context)
    51
    0
    {
    52
    0
      return _ccv_nnc_all_to_all_forw_cpu_ref(cmd, hint, flags, inputs, input_size, outputs, output_size, stream_context);
    53
    0
    }
    54
    55
    REGISTER_COMMAND_BACKEND(CCV_NNC_COMM_ALL_TO_ALL_FORWARD, CCV_NNC_BACKEND_CPU_REF)(ccv_nnc_cmd_backend_registry_t* const registry)
    56
    1
    {
    57
    1
      registry->tensor_formats = CCV_TENSOR_FORMAT_NHWC | CCV_TENSOR_FORMAT_NCHW | CCV_TENSOR_FORMAT_CHWN;
    58
    1
      registry->tensor_datatypes = CCV_64F | CCV_32F | CCV_16F | CCV_32S | CCV_8U;
    59
    1
      registry->tensor_memory = CCV_TENSOR_CPU_MEMORY;
    60
    1
      registry->algorithms = 1;
    61
    1
      registry->exec = _ccv_nnc_all_to_all_forw_cpu_ref;
    62
    1
    }
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    64
    REGISTER_COMMAND_BACKEND(CCV_NNC_COMM_ALL_TO_ALL_BACKWARD, CCV_NNC_BACKEND_CPU_REF)(ccv_nnc_cmd_backend_registry_t* const registry)
    65
    1
    {
    66
    1
      registry->tensor_formats = CCV_TENSOR_FORMAT_NHWC | CCV_TENSOR_FORMAT_NCHW | CCV_TENSOR_FORMAT_CHWN;
    67
    1
      registry->tensor_datatypes = CCV_64F | CCV_32F | CCV_16F | CCV_32S | CCV_8U;
    68
    1
      registry->tensor_memory = CCV_TENSOR_CPU_MEMORY;
    69
    1
      registry->algorithms = 1;
    70
    1
      registry->exec = _ccv_nnc_all_to_all_back_cpu_ref;
    71
    1
    }