#include "case.h"

#include "ccv_case.h"

#include "ccv_nnc_case.h"

#include <ccv.h>

#include <nnc/ccv_nnc.h>

#include <nnc/ccv_nnc_easy.h>

#include <3rdparty/dsfmt/dSFMT.h>

#include <nnc/ccv_nnc_internal.h>

#include <math.h>

TEST_SETUP()

{

  ccv_nnc_init();

}

#define INPUT_DIM (3)

#define OUTPUT_DIM (96)

#define INPUT_SIZE (224)

#define OUTPUT_SIZE (112)

#define KERNEL_SIZE (7)

#define BATCH_SIZE (16)

#define LN_DIM (10)

#define GN_C_DIM (16)

#define GN_RC_DIM (4)

TEST_CASE("mps forward convolution")

{

  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_CONVOLUTION_FORWARD, CCV_NNC_BACKEND_MPS));

  ccv_nnc_tensor_t* a = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, BATCH_SIZE, INPUT_SIZE, INPUT_SIZE, INPUT_DIM), 0);

  ccv_nnc_tensor_t* b = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, BATCH_SIZE, OUTPUT_SIZE, OUTPUT_SIZE, OUTPUT_DIM), 0);

  ccv_nnc_cmd_t cmd = CMD_CONVOLUTION_FORWARD(1, OUTPUT_DIM, KERNEL_SIZE, KERNEL_SIZE, INPUT_DIM);

  cmd.backend = CCV_NNC_BACKEND_CPU_REF;

  assert(cmd.backend >= 0);

  ccv_nnc_hint_t hint = ccv_nnc_hint_auto(cmd.info, a->info, b->info);

  assert(ccv_nnc_hint_verify(hint, cmd.info, a->info, b->info) == 0);

  ccv_nnc_tensor_t* w = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, OUTPUT_DIM, KERNEL_SIZE, KERNEL_SIZE, INPUT_DIM), 0);

  ccv_nnc_tensor_t* bias = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, OUTPUT_DIM), 0);

  // configure the inlets.

  dsfmt_t dsfmt;

  dsfmt_init_gen_rand(&dsfmt, 0);

  int i;

  for (i = 0; i < INPUT_DIM * KERNEL_SIZE * KERNEL_SIZE * OUTPUT_DIM; i++)

    w->data.f32[i] = dsfmt_genrand_open_close(&dsfmt) / (INPUT_DIM * KERNEL_SIZE * KERNEL_SIZE);

  for (i = 0; i < INPUT_SIZE * INPUT_SIZE * INPUT_DIM * ccv_max(1, BATCH_SIZE); i++)

    a->data.f32[i] = dsfmt_genrand_open_close(&dsfmt);

  for (i = 0; i < OUTPUT_DIM; i++)

    bias->data.f32[i] = (float)i / OUTPUT_DIM;

  // Copy generated matrix values over to GPU.

  ccv_nnc_tensor_t* ga = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, BATCH_SIZE, INPUT_SIZE, INPUT_SIZE, INPUT_DIM), 0);

  ccv_nnc_tensor_t* gw = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, OUTPUT_DIM, KERNEL_SIZE, KERNEL_SIZE, INPUT_DIM), 0);

  ccv_nnc_tensor_t* gwo = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, OUTPUT_DIM, INPUT_DIM, KERNEL_SIZE, KERNEL_SIZE), 0);

  ccv_nnc_tensor_t* gbias = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, OUTPUT_DIM), 0);

  ccv_nnc_cmd_t move = CMD_DATA_TRANSFER_FORWARD();

  move.backend = CCV_NNC_BACKEND_MPS;

  assert(move.backend >= 0);

  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, TENSOR_LIST(a, w, bias), TENSOR_LIST(ga, gw, gbias), 0);

  ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(a, w, bias), TENSOR_LIST(b), 0);

  ccv_nnc_tensor_t* gc = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, BATCH_SIZE, OUTPUT_SIZE, OUTPUT_SIZE, OUTPUT_DIM), 0);

  ccv_nnc_cmd_t transform = CMD_FORMAT_TRANSFORM_FORWARD();

  transform.backend = CCV_NNC_BACKEND_MPS;

  assert(transform.backend >= 0);

  ccv_nnc_stream_context_t* stream_context = ccv_nnc_stream_context_new(CCV_STREAM_CONTEXT_GPU);

  ccv_nnc_cmd_exec(transform, ccv_nnc_no_hint, 0, TENSOR_LIST(gw), TENSOR_LIST(gwo), stream_context);

  ccv_nnc_stream_context_wait(stream_context);

  ccv_nnc_tensor_free(gw);

  cmd.backend = CCV_NNC_BACKEND_MPS;

  assert(cmd.backend >= 0);

  cmd.algorithm = -1;

  cmd = ccv_nnc_cmd_autotune(cmd, 1 * 1024 * 1024 * 1024, hint, 0, TENSOR_LIST(ga, gwo, gbias), TENSOR_LIST(gc), stream_context);

  assert(CCV_NNC_EXEC_SUCCESS == ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(ga, gwo, gbias), TENSOR_LIST(gc), stream_context));

  ccv_nnc_stream_context_wait(stream_context);

  ccv_nnc_stream_context_free(stream_context);

  ccv_nnc_tensor_t* c = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, BATCH_SIZE, OUTPUT_SIZE, OUTPUT_SIZE, OUTPUT_DIM), 0);

  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, TENSOR_LIST(gc), TENSOR_LIST(c), 0);

  REQUIRE_ARRAY_EQ_WITH_TOLERANCE(float, b->data.f32, c->data.f32, OUTPUT_DIM * OUTPUT_SIZE * OUTPUT_SIZE, 5e-4, "output from mps should match from CPU");

  ccv_nnc_tensor_free(c);

  ccv_nnc_tensor_free(gc);

  ccv_nnc_tensor_free(bias);

  ccv_nnc_tensor_free(w);

  ccv_nnc_tensor_free(b);

  ccv_nnc_tensor_free(a);

  ccv_nnc_tensor_free(gbias);

  ccv_nnc_tensor_free(gwo);

  ccv_nnc_tensor_free(ga);

}

TEST_CASE("mps forward convolution in nchw format")

{

  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_CONVOLUTION_FORWARD, CCV_NNC_BACKEND_MPS));

  ccv_nnc_tensor_t* a = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, BATCH_SIZE, INPUT_DIM, INPUT_SIZE, INPUT_SIZE), 0);

  ccv_nnc_tensor_t* b = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, BATCH_SIZE, OUTPUT_DIM, OUTPUT_SIZE, OUTPUT_SIZE), 0);

  ccv_nnc_cmd_t cmd = CMD_CONVOLUTION_FORWARD(1, OUTPUT_DIM, KERNEL_SIZE, KERNEL_SIZE, INPUT_DIM);

  cmd.backend = CCV_NNC_BACKEND_CPU_REF;

  assert(cmd.backend >= 0);

  ccv_nnc_hint_t hint = ccv_nnc_hint_auto(cmd.info, a->info, b->info);

  assert(ccv_nnc_hint_verify(hint, cmd.info, a->info, b->info) == 0);

  ccv_nnc_tensor_t* w = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, OUTPUT_DIM, INPUT_DIM, KERNEL_SIZE, KERNEL_SIZE), 0);

  ccv_nnc_tensor_t* bias = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, OUTPUT_DIM), 0);

  // configure the inlets.

  dsfmt_t dsfmt;

  dsfmt_init_gen_rand(&dsfmt, 0);

  int i;

  for (i = 0; i < INPUT_DIM * KERNEL_SIZE * KERNEL_SIZE * OUTPUT_DIM; i++)

    w->data.f32[i] = dsfmt_genrand_open_close(&dsfmt) / (INPUT_DIM * KERNEL_SIZE * KERNEL_SIZE);

  for (i = 0; i < INPUT_SIZE * INPUT_SIZE * INPUT_DIM * ccv_max(1, BATCH_SIZE); i++)

    a->data.f32[i] = dsfmt_genrand_open_close(&dsfmt);

  for (i = 0; i < OUTPUT_DIM; i++)

    bias->data.f32[i] = (float)i / OUTPUT_DIM;

  // Copy generated matrix values over to GPU.

  ccv_nnc_tensor_t* ga = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, BATCH_SIZE, INPUT_DIM, INPUT_SIZE, INPUT_SIZE), 0);

  ccv_nnc_tensor_t* gw = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, OUTPUT_DIM, INPUT_DIM, KERNEL_SIZE, KERNEL_SIZE), 0);

  ccv_nnc_tensor_t* gbias = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, OUTPUT_DIM), 0);

  ccv_nnc_cmd_t move = CMD_DATA_TRANSFER_FORWARD();

  move.backend = CCV_NNC_BACKEND_MPS;

  assert(move.backend >= 0);

  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, TENSOR_LIST(a, w, bias), TENSOR_LIST(ga, gw, gbias), 0);

  ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(a, w, bias), TENSOR_LIST(b), 0);

  ccv_nnc_tensor_t* gc = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, BATCH_SIZE, OUTPUT_DIM, OUTPUT_SIZE, OUTPUT_SIZE), 0);

  ccv_nnc_cmd_t transform = CMD_FORMAT_TRANSFORM_FORWARD();

  transform.backend = CCV_NNC_BACKEND_MPS;

  assert(transform.backend >= 0);

  cmd.backend = CCV_NNC_BACKEND_MPS;

  assert(cmd.backend >= 0);

  cmd.algorithm = -1;

  cmd = ccv_nnc_cmd_autotune(cmd, 1 * 1024 * 1024 * 1024, hint, 0, TENSOR_LIST(ga, gw, gbias), TENSOR_LIST(gc), 0);

  assert(CCV_NNC_EXEC_SUCCESS == ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(ga, gw, gbias), TENSOR_LIST(gc), 0));

  ccv_nnc_tensor_t* c = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, BATCH_SIZE, OUTPUT_DIM, OUTPUT_SIZE, OUTPUT_SIZE), 0);

  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, TENSOR_LIST(gc), TENSOR_LIST(c), 0);

  REQUIRE_ARRAY_EQ_WITH_TOLERANCE(float, b->data.f32, c->data.f32, OUTPUT_DIM * OUTPUT_SIZE * OUTPUT_SIZE, 1e-3, "output from mps should match from CPU");

  ccv_nnc_tensor_free(c);

  ccv_nnc_tensor_free(gc);

  ccv_nnc_tensor_free(bias);

  ccv_nnc_tensor_free(w);

  ccv_nnc_tensor_free(b);

  ccv_nnc_tensor_free(a);

  ccv_nnc_tensor_free(gbias);

  ccv_nnc_tensor_free(gw);

  ccv_nnc_tensor_free(ga);

}

TEST_CASE("mps forward grouped convolution falls back with mfa enabled")

{

  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_CONVOLUTION_FORWARD, CCV_NNC_BACKEND_MPS));

  const int groups = 2;

  const int input_dim = 4;

  const int output_dim = 6;

  const int batch_size = 2;

  const int input_size = 8;

  const int kernel_size = 3;

  const int output_size = input_size - kernel_size + 1;

  ccv_nnc_tensor_t* a = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, batch_size, input_dim, input_size, input_size), 0);

  ccv_nnc_tensor_t* b = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, batch_size, output_dim, output_size, output_size), 0);

  ccv_nnc_tensor_t* w = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, output_dim, input_dim / groups, kernel_size, kernel_size), 0);

  ccv_nnc_cmd_t cmd = CMD_CONVOLUTION_FORWARD(groups, output_dim, kernel_size, kernel_size, input_dim / groups);

  ccv_nnc_hint_t hint = HINT((1, 1), (0, 0));

  dsfmt_t dsfmt;

  dsfmt_init_gen_rand(&dsfmt, 0);

  int i;

  for (i = 0; i < batch_size * input_dim * input_size * input_size; i++)

    a->data.f32[i] = dsfmt_genrand_open_close(&dsfmt);

  for (i = 0; i < output_dim * (input_dim / groups) * kernel_size * kernel_size; i++)

    w->data.f32[i] = dsfmt_genrand_open_close(&dsfmt) / (input_dim / groups * kernel_size * kernel_size);

  ccv_nnc_cmd_t cpu_cmd = cmd;

  cpu_cmd.backend = CCV_NNC_BACKEND_CPU_REF;

  assert(cpu_cmd.backend >= 0);

  ccv_nnc_cmd_exec(cpu_cmd, hint, 0, TENSOR_LIST(a, w), TENSOR_LIST(b), 0);

  ccv_nnc_tensor_t* ga = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, batch_size, input_dim, input_size, input_size), 0);

  ccv_nnc_tensor_t* gw = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, output_dim, input_dim / groups, kernel_size, kernel_size), 0);

  ccv_nnc_tensor_t* gc = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, batch_size, output_dim, output_size, output_size), 0);

  ccv_nnc_cmd_t move = CMD_DATA_TRANSFER_FORWARD();

  move.backend = CCV_NNC_BACKEND_MPS;

  assert(move.backend >= 0);

  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, TENSOR_LIST(a, w), TENSOR_LIST(ga, gw), 0);

  ccv_nnc_cmd_t mps_cmd = cmd;

  mps_cmd.backend = CCV_NNC_BACKEND_MPS;

  assert(mps_cmd.backend >= 0);

  assert(CCV_NNC_EXEC_SUCCESS == ccv_nnc_cmd_exec(mps_cmd, hint, 0, TENSOR_LIST(ga, gw), TENSOR_LIST(gc), 0));

  ccv_nnc_tensor_t* c = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, batch_size, output_dim, output_size, output_size), 0);

  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, TENSOR_LIST(gc), TENSOR_LIST(c), 0);

  REQUIRE_ARRAY_EQ_WITH_TOLERANCE(float, b->data.f32, c->data.f32, batch_size * output_dim * output_size * output_size, 1e-5, "grouped convolution output from mps should match from CPU");

  ccv_nnc_tensor_free(c);

  ccv_nnc_tensor_free(gc);

  ccv_nnc_tensor_free(gw);

  ccv_nnc_tensor_free(ga);

  ccv_nnc_tensor_free(w);

  ccv_nnc_tensor_free(b);

  ccv_nnc_tensor_free(a);

}

TEST_CASE("mps forward convolution with 1x1 kernel")

{

  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_CONVOLUTION_FORWARD, CCV_NNC_BACKEND_MPS));

  ccv_nnc_tensor_t* a = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, BATCH_SIZE, OUTPUT_SIZE, OUTPUT_SIZE, INPUT_DIM), 0);

  ccv_nnc_tensor_t* b = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, BATCH_SIZE, OUTPUT_SIZE, OUTPUT_SIZE, OUTPUT_DIM), 0);

  ccv_nnc_cmd_t cmd = CMD_CONVOLUTION_FORWARD(1, OUTPUT_DIM, 1, 1, INPUT_DIM);

  cmd.backend = CCV_NNC_BACKEND_CPU_REF;

  assert(cmd.backend >= 0);

  ccv_nnc_hint_t hint = ccv_nnc_hint_auto(cmd.info, a->info, b->info);

  assert(ccv_nnc_hint_verify(hint, cmd.info, a->info, b->info) == 0);

  ccv_nnc_tensor_t* w = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, OUTPUT_DIM, 1, 1, INPUT_DIM), 0);

  ccv_nnc_tensor_t* bias = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, OUTPUT_DIM), 0);

  // configure the inlets.

  dsfmt_t dsfmt;

  dsfmt_init_gen_rand(&dsfmt, 0);

  int i;

  for (i = 0; i < INPUT_DIM * 1 * 1 * OUTPUT_DIM; i++)

    w->data.f32[i] = dsfmt_genrand_open_close(&dsfmt) / (INPUT_DIM * 1 * 1);

  for (i = 0; i < OUTPUT_SIZE * OUTPUT_SIZE * INPUT_DIM * ccv_max(1, BATCH_SIZE); i++)

    a->data.f32[i] = dsfmt_genrand_open_close(&dsfmt);

  for (i = 0; i < OUTPUT_DIM; i++)

    bias->data.f32[i] = (float)i / OUTPUT_DIM;

  // Copy generated matrix values over to GPU.

  ccv_nnc_tensor_t* ga = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, BATCH_SIZE, OUTPUT_SIZE, OUTPUT_SIZE, INPUT_DIM), 0);

  ccv_nnc_tensor_t* gw = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, OUTPUT_DIM, 1, 1, INPUT_DIM), 0);

  ccv_nnc_tensor_t* gwo = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, OUTPUT_DIM, INPUT_DIM, 1, 1), 0);

  ccv_nnc_tensor_t* gbias = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, OUTPUT_DIM), 0);

  ccv_nnc_cmd_t move = CMD_DATA_TRANSFER_FORWARD();

  move.backend = CCV_NNC_BACKEND_MPS;

  assert(move.backend >= 0);

  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, TENSOR_LIST(a, w, bias), TENSOR_LIST(ga, gw, gbias), 0);

  ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(a, w, bias), TENSOR_LIST(b), 0);

  ccv_nnc_tensor_t* gc = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 32F, BATCH_SIZE, OUTPUT_SIZE, OUTPUT_SIZE, OUTPUT_DIM), 0);

  ccv_nnc_cmd_t transform = CMD_FORMAT_TRANSFORM_FORWARD();

  transform.backend = CCV_NNC_BACKEND_MPS;

  assert(transform.backend >= 0);

  ccv_nnc_stream_context_t* stream_context = ccv_nnc_stream_context_new(CCV_STREAM_CONTEXT_GPU);

  ccv_nnc_cmd_exec(transform, ccv_nnc_no_hint, 0, TENSOR_LIST(gw), TENSOR_LIST(gwo), stream_context);

  ccv_nnc_stream_context_wait(stream_context);

  ccv_nnc_tensor_free(gw);

  cmd.backend = CCV_NNC_BACKEND_MPS;

  assert(cmd.backend >= 0);

  cmd.algorithm = -1;

  cmd = ccv_nnc_cmd_autotune(cmd, 1 * 1024 * 1024 * 1024, hint, 0, TENSOR_LIST(ga, gwo, gbias), TENSOR_LIST(gc), stream_context);

  assert(CCV_NNC_EXEC_SUCCESS == ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(ga, gwo, gbias), TENSOR_LIST(gc), stream_context));

  ccv_nnc_stream_context_wait(stream_context);

  ccv_nnc_stream_context_free(stream_context);

  ccv_nnc_tensor_t* c = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, BATCH_SIZE, OUTPUT_SIZE, OUTPUT_SIZE, OUTPUT_DIM), 0);

  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, TENSOR_LIST(gc), TENSOR_LIST(c), 0);

  REQUIRE_ARRAY_EQ_WITH_TOLERANCE(float, b->data.f32, c->data.f32, OUTPUT_DIM * OUTPUT_SIZE * OUTPUT_SIZE, 1e-3, "output from mps should match from CPU");

  ccv_nnc_tensor_free(c);

  ccv_nnc_tensor_free(gc);

  ccv_nnc_tensor_free(bias);

  ccv_nnc_tensor_free(w);

  ccv_nnc_tensor_free(b);

  ccv_nnc_tensor_free(a);

  ccv_nnc_tensor_free(gbias);

  ccv_nnc_tensor_free(gwo);

  ccv_nnc_tensor_free(ga);

}

TEST_CASE("mps forward convolution in nchw format with 1x1 kernel")

{

  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_CONVOLUTION_FORWARD, CCV_NNC_BACKEND_MPS));

  ccv_nnc_tensor_t* a = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, BATCH_SIZE, INPUT_DIM, OUTPUT_SIZE, OUTPUT_SIZE), 0);

  ccv_nnc_tensor_t* b = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, BATCH_SIZE, OUTPUT_DIM, OUTPUT_SIZE, OUTPUT_SIZE), 0);

  ccv_nnc_cmd_t cmd = CMD_CONVOLUTION_FORWARD(1, OUTPUT_DIM, 1, 1, INPUT_DIM);

  cmd.backend = CCV_NNC_BACKEND_CPU_REF;

  assert(cmd.backend >= 0);

  ccv_nnc_hint_t hint = ccv_nnc_hint_auto(cmd.info, a->info, b->info);

  assert(ccv_nnc_hint_verify(hint, cmd.info, a->info, b->info) == 0);

  ccv_nnc_tensor_t* w = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, OUTPUT_DIM, INPUT_DIM, 1, 1), 0);

  ccv_nnc_tensor_t* bias = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, OUTPUT_DIM), 0);

  // configure the inlets.

  dsfmt_t dsfmt;

  dsfmt_init_gen_rand(&dsfmt, 0);

  int i;

  for (i = 0; i < INPUT_DIM * 1 * 1 * OUTPUT_DIM; i++)

    w->data.f32[i] = dsfmt_genrand_open_close(&dsfmt) / (INPUT_DIM * 1 * 1);

  for (i = 0; i < OUTPUT_SIZE * OUTPUT_SIZE * INPUT_DIM * ccv_max(1, BATCH_SIZE); i++)

    a->data.f32[i] = dsfmt_genrand_open_close(&dsfmt);

  for (i = 0; i < OUTPUT_DIM; i++)

    bias->data.f32[i] = (float)i / OUTPUT_DIM;

  // Copy generated matrix values over to GPU.

  ccv_nnc_tensor_t* ga = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, BATCH_SIZE, INPUT_DIM, OUTPUT_SIZE, OUTPUT_SIZE), 0);

  ccv_nnc_tensor_t* gw = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, OUTPUT_DIM, INPUT_DIM, 1, 1), 0);

  ccv_nnc_tensor_t* gbias = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, OUTPUT_DIM), 0);

  ccv_nnc_cmd_t move = CMD_DATA_TRANSFER_FORWARD();

  move.backend = CCV_NNC_BACKEND_MPS;

  assert(move.backend >= 0);

  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, TENSOR_LIST(a, w, bias), TENSOR_LIST(ga, gw, gbias), 0);

  ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(a, w, bias), TENSOR_LIST(b), 0);

  ccv_nnc_tensor_t* gc = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, BATCH_SIZE, OUTPUT_DIM, OUTPUT_SIZE, OUTPUT_SIZE), 0);

  ccv_nnc_cmd_t transform = CMD_FORMAT_TRANSFORM_FORWARD();

  transform.backend = CCV_NNC_BACKEND_MPS;

  assert(transform.backend >= 0);

  cmd.backend = CCV_NNC_BACKEND_MPS;

  assert(cmd.backend >= 0);

  cmd.algorithm = -1;

  cmd = ccv_nnc_cmd_autotune(cmd, 1 * 1024 * 1024 * 1024, hint, 0, TENSOR_LIST(ga, gw, gbias), TENSOR_LIST(gc), 0);

  assert(CCV_NNC_EXEC_SUCCESS == ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(ga, gw, gbias), TENSOR_LIST(gc), 0));

  ccv_nnc_tensor_t* c = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, BATCH_SIZE, OUTPUT_DIM, OUTPUT_SIZE, OUTPUT_SIZE), 0);

  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, TENSOR_LIST(gc), TENSOR_LIST(c), 0);

  REQUIRE_ARRAY_EQ_WITH_TOLERANCE(float, b->data.f32, c->data.f32, OUTPUT_DIM * OUTPUT_SIZE * OUTPUT_SIZE, 1e-3, "output from mps should match from CPU");

  ccv_nnc_tensor_free(c);

  ccv_nnc_tensor_free(gc);

  ccv_nnc_tensor_free(bias);

  ccv_nnc_tensor_free(w);

  ccv_nnc_tensor_free(b);

  ccv_nnc_tensor_free(a);

  ccv_nnc_tensor_free(gbias);

  ccv_nnc_tensor_free(gw);

  ccv_nnc_tensor_free(ga);

}

TEST_CASE("mps forward convolution in nchw format with row-wise 8i weight")

{

  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_CONVOLUTION_FORWARD, CCV_NNC_BACKEND_MPS));

  const int batch_size = 2;

  const int input_dim = 8;

  const int output_dim = 12;

  const int spatial = 9;

  ccv_nnc_tensor_t* a = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, batch_size, input_dim, spatial, spatial), 0);

  ccv_nnc_tensor_t* b = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, batch_size, output_dim, spatial, spatial), 0);

  ccv_nnc_cmd_t cmd = CMD_CONVOLUTION_FORWARD(1, output_dim, 1, 1, input_dim);

  cmd.backend = CCV_NNC_BACKEND_CPU_REF;

  assert(cmd.backend >= 0);

  ccv_nnc_hint_t hint = ccv_nnc_hint_auto(cmd.info, a->info, b->info);

  assert(ccv_nnc_hint_verify(hint, cmd.info, a->info, b->info) == 0);

  ccv_nnc_tensor_t* w = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, output_dim, input_dim, 1, 1), 0);

  ccv_nnc_tensor_t* wq = ccv_nnc_tensor_new(0, ccv_nnc_tensor_8i_rowwise(CPU_TENSOR_NCHW(32F, output_dim, input_dim, 1, 1)), 0);

  ccv_nnc_tensor_t* bias = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, output_dim), 0);

  dsfmt_t dsfmt;

  dsfmt_init_gen_rand(&dsfmt, 0);

  int i;

  for (i = 0; i < batch_size * input_dim * spatial * spatial; i++)

    a->data.f32[i] = dsfmt_genrand_open_close(&dsfmt);

  for (i = 0; i < output_dim * input_dim; i++)

    w->data.f32[i] = dsfmt_genrand_open_close(&dsfmt) - 0.5f;

  for (i = 0; i < output_dim; i++)

    bias->data.f32[i] = (float)i / output_dim;

  const size_t qsize = ccv_nnc_quantize_8i_rowwise(w->data.f32, CCV_32F, CCV_TENSOR_CPU_MEMORY, output_dim * input_dim, 1, wq->data.u8, ccv_nnc_tensor_data_size_without_padding(wq->info));

  REQUIRE_EQ(qsize, ccv_nnc_tensor_data_size_without_padding(wq->info), "row-wise 8i convolution weight should fit the tensor exactly");

  ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(a, w, bias), TENSOR_LIST(b), 0);

  ccv_nnc_tensor_t* ga = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, batch_size, input_dim, spatial, spatial), 0);

  ccv_nnc_tensor_t* gwq = ccv_nnc_tensor_new(0, ccv_nnc_tensor_8i_rowwise(GPU_TENSOR_NCHW(000, 32F, output_dim, input_dim, 1, 1)), 0);

  ccv_nnc_tensor_t* gbias = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, output_dim), 0);

  ccv_nnc_tensor_t* gc = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, batch_size, output_dim, spatial, spatial), 0);

  ccv_nnc_cmd_t move = CMD_DATA_TRANSFER_FORWARD();

  move.backend = CCV_NNC_BACKEND_MPS;

  assert(move.backend >= 0);

  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, TENSOR_LIST(a, wq, bias), TENSOR_LIST(ga, gwq, gbias), 0);

  cmd.backend = CCV_NNC_BACKEND_MPS;

  assert(cmd.backend >= 0);

  cmd.algorithm = -1;

  cmd = ccv_nnc_cmd_autotune(cmd, 1 * 1024 * 1024 * 1024, hint, 0, TENSOR_LIST(ga, gwq, gbias), TENSOR_LIST(gc), 0);

  assert(CCV_NNC_EXEC_SUCCESS == ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(ga, gwq, gbias), TENSOR_LIST(gc), 0));

  ccv_nnc_tensor_t* c = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, batch_size, output_dim, spatial, spatial), 0);

  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, TENSOR_LIST(gc), TENSOR_LIST(c), 0);

  REQUIRE_ARRAY_EQ_WITH_TOLERANCE(float, b->data.f32, c->data.f32, batch_size * output_dim * spatial * spatial, 2e-3, "output from mps should match CPU when row-wise 8i weights are dequantized to dense scratch");

  ccv_nnc_tensor_free(c);

  ccv_nnc_tensor_free(gc);

  ccv_nnc_tensor_free(gbias);

  ccv_nnc_tensor_free(gwq);

  ccv_nnc_tensor_free(ga);

  ccv_nnc_tensor_free(bias);

  ccv_nnc_tensor_free(wq);

  ccv_nnc_tensor_free(w);

  ccv_nnc_tensor_free(b);

  ccv_nnc_tensor_free(a);

}

TEST_CASE("mps forward convolution in nchw format with 1x1 kernel and no bias")

{

  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_CONVOLUTION_FORWARD, CCV_NNC_BACKEND_MPS));

  ccv_nnc_tensor_t* a = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, BATCH_SIZE, INPUT_DIM, OUTPUT_SIZE, OUTPUT_SIZE), 0);

  ccv_nnc_tensor_t* b = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, BATCH_SIZE, OUTPUT_DIM, OUTPUT_SIZE, OUTPUT_SIZE), 0);

  ccv_nnc_cmd_t cmd = CMD_CONVOLUTION_FORWARD(1, OUTPUT_DIM, 1, 1, INPUT_DIM);

  cmd.backend = CCV_NNC_BACKEND_CPU_REF;

  assert(cmd.backend >= 0);

  ccv_nnc_hint_t hint = ccv_nnc_hint_auto(cmd.info, a->info, b->info);

  assert(ccv_nnc_hint_verify(hint, cmd.info, a->info, b->info) == 0);

  ccv_nnc_tensor_t* w = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, OUTPUT_DIM, INPUT_DIM, 1, 1), 0);

  dsfmt_t dsfmt;

  dsfmt_init_gen_rand(&dsfmt, 1);

  int i;

  for (i = 0; i < INPUT_DIM * 1 * 1 * OUTPUT_DIM; i++)

    w->data.f32[i] = dsfmt_genrand_open_close(&dsfmt) / (INPUT_DIM * 1 * 1);

  for (i = 0; i < OUTPUT_SIZE * OUTPUT_SIZE * INPUT_DIM * ccv_max(1, BATCH_SIZE); i++)

    a->data.f32[i] = dsfmt_genrand_open_close(&dsfmt);

  ccv_nnc_tensor_t* ga = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, BATCH_SIZE, INPUT_DIM, OUTPUT_SIZE, OUTPUT_SIZE), 0);

  ccv_nnc_tensor_t* gw = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, OUTPUT_DIM, INPUT_DIM, 1, 1), 0);

  ccv_nnc_cmd_t move = CMD_DATA_TRANSFER_FORWARD();

  move.backend = CCV_NNC_BACKEND_MPS;

  assert(move.backend >= 0);

  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, TENSOR_LIST(a, w), TENSOR_LIST(ga, gw), 0);

  ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(a, w), TENSOR_LIST(b), 0);

  ccv_nnc_tensor_t* gc = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, BATCH_SIZE, OUTPUT_DIM, OUTPUT_SIZE, OUTPUT_SIZE), 0);

  cmd.backend = CCV_NNC_BACKEND_MPS;

  assert(cmd.backend >= 0);

  cmd.algorithm = -1;

  cmd = ccv_nnc_cmd_autotune(cmd, 1 * 1024 * 1024 * 1024, hint, 0, TENSOR_LIST(ga, gw), TENSOR_LIST(gc), 0);

  assert(CCV_NNC_EXEC_SUCCESS == ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(ga, gw), TENSOR_LIST(gc), 0));

  ccv_nnc_tensor_t* c = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, BATCH_SIZE, OUTPUT_DIM, OUTPUT_SIZE, OUTPUT_SIZE), 0);

  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, TENSOR_LIST(gc), TENSOR_LIST(c), 0);

  REQUIRE_ARRAY_EQ_WITH_TOLERANCE(float, b->data.f32, c->data.f32, OUTPUT_DIM * OUTPUT_SIZE * OUTPUT_SIZE, 1e-3, "output from mps should match from CPU");

  ccv_nnc_tensor_free(c);

  ccv_nnc_tensor_free(gc);

  ccv_nnc_tensor_free(w);

  ccv_nnc_tensor_free(b);

  ccv_nnc_tensor_free(a);

  ccv_nnc_tensor_free(gw);

  ccv_nnc_tensor_free(ga);

}

TEST_CASE("mps forward convolution in nchw format with 1x1 kernel on edge tiles")

{

  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_CONVOLUTION_FORWARD, CCV_NNC_BACKEND_MPS));

  const int batch_size = 2;

  const int input_dim = 17;

  const int output_dim = 77;

  const int output_h = 17;

  const int output_w = 19;

  ccv_nnc_tensor_t* a = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, batch_size, input_dim, output_h, output_w), 0);

  ccv_nnc_tensor_t* b = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, batch_size, output_dim, output_h, output_w), 0);

  ccv_nnc_cmd_t cmd = CMD_CONVOLUTION_FORWARD(1, output_dim, 1, 1, input_dim);

  cmd.backend = CCV_NNC_BACKEND_CPU_REF;

  assert(cmd.backend >= 0);

  ccv_nnc_hint_t hint = ccv_nnc_hint_auto(cmd.info, a->info, b->info);

  assert(ccv_nnc_hint_verify(hint, cmd.info, a->info, b->info) == 0);

  ccv_nnc_tensor_t* w = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, output_dim, input_dim, 1, 1), 0);

  ccv_nnc_tensor_t* bias = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, output_dim), 0);

  dsfmt_t dsfmt;

  dsfmt_init_gen_rand(&dsfmt, 2);

  int i;

  for (i = 0; i < input_dim * output_dim; i++)

    w->data.f32[i] = dsfmt_genrand_open_close(&dsfmt) / input_dim;

  for (i = 0; i < batch_size * input_dim * output_h * output_w; i++)

    a->data.f32[i] = dsfmt_genrand_open_close(&dsfmt);

  for (i = 0; i < output_dim; i++)

    bias->data.f32[i] = (float)i / output_dim;

  ccv_nnc_tensor_t* ga = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, batch_size, input_dim, output_h, output_w), 0);

  ccv_nnc_tensor_t* gw = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, output_dim, input_dim, 1, 1), 0);

  ccv_nnc_tensor_t* gbias = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, output_dim), 0);

  ccv_nnc_cmd_t move = CMD_DATA_TRANSFER_FORWARD();

  move.backend = CCV_NNC_BACKEND_MPS;

  assert(move.backend >= 0);

  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, TENSOR_LIST(a, w, bias), TENSOR_LIST(ga, gw, gbias), 0);

  ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(a, w, bias), TENSOR_LIST(b), 0);

  ccv_nnc_tensor_t* gc = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, batch_size, output_dim, output_h, output_w), 0);

  cmd.backend = CCV_NNC_BACKEND_MPS;

  assert(cmd.backend >= 0);

  cmd.algorithm = -1;

  cmd = ccv_nnc_cmd_autotune(cmd, 1 * 1024 * 1024 * 1024, hint, 0, TENSOR_LIST(ga, gw, gbias), TENSOR_LIST(gc), 0);

  assert(CCV_NNC_EXEC_SUCCESS == ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(ga, gw, gbias), TENSOR_LIST(gc), 0));

  ccv_nnc_tensor_t* c = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, batch_size, output_dim, output_h, output_w), 0);

  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, TENSOR_LIST(gc), TENSOR_LIST(c), 0);

  REQUIRE_ARRAY_EQ_WITH_TOLERANCE(float, b->data.f32, c->data.f32, batch_size * output_dim * output_h * output_w, 1e-3, "output from mps should match from CPU");

  ccv_nnc_tensor_free(c);

  ccv_nnc_tensor_free(gc);

  ccv_nnc_tensor_free(bias);

  ccv_nnc_tensor_free(w);

  ccv_nnc_tensor_free(b);

  ccv_nnc_tensor_free(a);

  ccv_nnc_tensor_free(gbias);

  ccv_nnc_tensor_free(gw);

  ccv_nnc_tensor_free(ga);

}

TEST_CASE("mps forward convolution in nchw format with 1x1 kernel on edge tiles and no bias")

{

  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_CONVOLUTION_FORWARD, CCV_NNC_BACKEND_MPS));

  const int batch_size = 2;

  const int input_dim = 17;

  const int output_dim = 77;

  const int output_h = 17;

  const int output_w = 19;

  ccv_nnc_tensor_t* a = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, batch_size, input_dim, output_h, output_w), 0);

  ccv_nnc_tensor_t* b = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, batch_size, output_dim, output_h, output_w), 0);

  ccv_nnc_cmd_t cmd = CMD_CONVOLUTION_FORWARD(1, output_dim, 1, 1, input_dim);

  cmd.backend = CCV_NNC_BACKEND_CPU_REF;

  assert(cmd.backend >= 0);

  ccv_nnc_hint_t hint = ccv_nnc_hint_auto(cmd.info, a->info, b->info);

  assert(ccv_nnc_hint_verify(hint, cmd.info, a->info, b->info) == 0);

  ccv_nnc_tensor_t* w = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, output_dim, input_dim, 1, 1), 0);

  dsfmt_t dsfmt;

  dsfmt_init_gen_rand(&dsfmt, 3);

  int i;

  for (i = 0; i < input_dim * output_dim; i++)

    w->data.f32[i] = dsfmt_genrand_open_close(&dsfmt) / input_dim;

  for (i = 0; i < batch_size * input_dim * output_h * output_w; i++)

    a->data.f32[i] = dsfmt_genrand_open_close(&dsfmt);

  ccv_nnc_tensor_t* ga = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, batch_size, input_dim, output_h, output_w), 0);

  ccv_nnc_tensor_t* gw = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, output_dim, input_dim, 1, 1), 0);

  ccv_nnc_cmd_t move = CMD_DATA_TRANSFER_FORWARD();

  move.backend = CCV_NNC_BACKEND_MPS;

  assert(move.backend >= 0);

  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, TENSOR_LIST(a, w), TENSOR_LIST(ga, gw), 0);

  ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(a, w), TENSOR_LIST(b), 0);

  ccv_nnc_tensor_t* gc = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 32F, batch_size, output_dim, output_h, output_w), 0);

  cmd.backend = CCV_NNC_BACKEND_MPS;

  assert(cmd.backend >= 0);

  cmd.algorithm = -1;

  cmd = ccv_nnc_cmd_autotune(cmd, 1 * 1024 * 1024 * 1024, hint, 0, TENSOR_LIST(ga, gw), TENSOR_LIST(gc), 0);

  assert(CCV_NNC_EXEC_SUCCESS == ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(ga, gw), TENSOR_LIST(gc), 0));

  ccv_nnc_tensor_t* c = ccv_nnc_tensor_new(0, CPU_TENSOR_NCHW(32F, batch_size, output_dim, output_h, output_w), 0);

  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, TENSOR_LIST(gc), TENSOR_LIST(c), 0);

  REQUIRE_ARRAY_EQ_WITH_TOLERANCE(float, b->data.f32, c->data.f32, batch_size * output_dim * output_h * output_w, 1e-3, "output from mps should match from CPU");

  ccv_nnc_tensor_free(c);

  ccv_nnc_tensor_free(gc);

  ccv_nnc_tensor_free(w);

  ccv_nnc_tensor_free(b);

  ccv_nnc_tensor_free(a);

  ccv_nnc_tensor_free(gw);

  ccv_nnc_tensor_free(ga);

}

TEST_CASE("mps forward convolution in half precision")

{

  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_CONVOLUTION_FORWARD, CCV_NNC_BACKEND_MPS));

  ccv_nnc_tensor_t* a = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, BATCH_SIZE, INPUT_SIZE, INPUT_SIZE, INPUT_DIM), 0);

  ccv_nnc_tensor_t* b = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, BATCH_SIZE, OUTPUT_SIZE, OUTPUT_SIZE, OUTPUT_DIM), 0);

  ccv_nnc_cmd_t cmd = CMD_CONVOLUTION_FORWARD(1, OUTPUT_DIM, KERNEL_SIZE, KERNEL_SIZE, INPUT_DIM);

  cmd.backend = CCV_NNC_BACKEND_CPU_REF;

  assert(cmd.backend >= 0);

  ccv_nnc_hint_t hint = ccv_nnc_hint_auto(cmd.info, a->info, b->info);

  assert(ccv_nnc_hint_verify(hint, cmd.info, a->info, b->info) == 0);

  ccv_nnc_tensor_t* w = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, OUTPUT_DIM, KERNEL_SIZE, KERNEL_SIZE, INPUT_DIM), 0);

  ccv_nnc_tensor_t* bias = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, OUTPUT_DIM), 0);

  // configure the inlets.

  dsfmt_t dsfmt;

  dsfmt_init_gen_rand(&dsfmt, 0);

  int i;

  for (i = 0; i < INPUT_DIM * KERNEL_SIZE * KERNEL_SIZE * OUTPUT_DIM; i++)

    w->data.f32[i] = dsfmt_genrand_open_close(&dsfmt) / (INPUT_DIM * KERNEL_SIZE * KERNEL_SIZE);

  for (i = 0; i < INPUT_SIZE * INPUT_SIZE * INPUT_DIM * ccv_max(1, BATCH_SIZE); i++)

    a->data.f32[i] = dsfmt_genrand_open_close(&dsfmt);

  for (i = 0; i < OUTPUT_DIM; i++)

    bias->data.f32[i] = (float)i / OUTPUT_DIM;

  ccv_nnc_tensor_t* a1 = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(16F, BATCH_SIZE, INPUT_SIZE, INPUT_SIZE, INPUT_DIM), 0);

  ccv_nnc_tensor_t* w1 = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(16F, OUTPUT_DIM, KERNEL_SIZE, KERNEL_SIZE, INPUT_DIM), 0);

  ccv_nnc_tensor_t* bias1 = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(16F, OUTPUT_DIM), 0);

  ccv_nnc_cmd_exec(CMD_DATATYPE_CONVERSION_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(a, w, bias), TENSOR_LIST(a1, w1, bias1), 0);

  // Copy generated matrix values over to GPU.

  ccv_nnc_tensor_t* ga = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 16F, BATCH_SIZE, INPUT_SIZE, INPUT_SIZE, INPUT_DIM), 0);

  ccv_nnc_tensor_t* gw = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 16F, OUTPUT_DIM, KERNEL_SIZE, KERNEL_SIZE, INPUT_DIM), 0);

  ccv_nnc_tensor_t* gwo = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 16F, OUTPUT_DIM, INPUT_DIM, KERNEL_SIZE, KERNEL_SIZE), 0);

  ccv_nnc_tensor_t* gbias = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 16F, OUTPUT_DIM), 0);

  ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(a1, w1, bias1), TENSOR_LIST(ga, gw, gbias), 0);

  ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(a, w, bias), TENSOR_LIST(b), 0);

  ccv_nnc_tensor_t* gc = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 16F, BATCH_SIZE, OUTPUT_SIZE, OUTPUT_SIZE, OUTPUT_DIM), 0);

  ccv_nnc_cmd_t transform = CMD_FORMAT_TRANSFORM_FORWARD();

  transform.backend = CCV_NNC_BACKEND_MPS;

  assert(transform.backend >= 0);

  ccv_nnc_stream_context_t* stream_context = ccv_nnc_stream_context_new(CCV_STREAM_CONTEXT_GPU);

  ccv_nnc_cmd_exec(transform, ccv_nnc_no_hint, 0, TENSOR_LIST(gw), TENSOR_LIST(gwo), stream_context);

  ccv_nnc_stream_context_wait(stream_context);

  ccv_nnc_tensor_free(gw);

  cmd.backend = CCV_NNC_BACKEND_MPS;

  assert(cmd.backend >= 0);

  cmd.algorithm = -1;

  cmd = ccv_nnc_cmd_autotune(cmd, 1 * 1024 * 1024 * 1024, hint, 0, TENSOR_LIST(ga, gwo, gbias), TENSOR_LIST(gc), stream_context);

  assert(CCV_NNC_EXEC_SUCCESS == ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(ga, gwo, gbias), TENSOR_LIST(gc), stream_context));

  ccv_nnc_stream_context_wait(stream_context);

  ccv_nnc_stream_context_free(stream_context);

  ccv_nnc_tensor_t* c1 = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(16F, BATCH_SIZE, OUTPUT_SIZE, OUTPUT_SIZE, OUTPUT_DIM), 0);

  ccv_nnc_cmd_exec(CMD_DATA_TRANSFER_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(gc), TENSOR_LIST(c1), 0);

  ccv_nnc_tensor_t* c = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, BATCH_SIZE, OUTPUT_SIZE, OUTPUT_SIZE, OUTPUT_DIM), 0);

  ccv_nnc_cmd_exec(CMD_DATATYPE_CONVERSION_FORWARD(), ccv_nnc_no_hint, 0, TENSOR_LIST(c1), TENSOR_LIST(c), 0);

  REQUIRE_ARRAY_EQ_WITH_TOLERANCE(float, b->data.f32, c->data.f32, OUTPUT_DIM * OUTPUT_SIZE * OUTPUT_SIZE, 5e-3, "output from mps should match from CPU");

  ccv_nnc_tensor_free(c);

  ccv_nnc_tensor_free(gc);

  ccv_nnc_tensor_free(bias);

  ccv_nnc_tensor_free(w);

  ccv_nnc_tensor_free(b);

  ccv_nnc_tensor_free(a);

  ccv_nnc_tensor_free(c1);

  ccv_nnc_tensor_free(bias1);

  ccv_nnc_tensor_free(w1);

  ccv_nnc_tensor_free(a1);

  ccv_nnc_tensor_free(gbias);

  ccv_nnc_tensor_free(gwo);

  ccv_nnc_tensor_free(ga);

}

TEST_CASE("mps forward convolution in bfloat precision")

{

  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_CONVOLUTION_FORWARD, CCV_NNC_BACKEND_MPS));

  const int batch_size = 2;

  const int input_size = 17;

  const int kernel_size = 3;

  const int output_size = 15;

  const int input_dim = 8;

  const int output_dim = 16;

  ccv_nnc_tensor_t* a = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, batch_size, input_size, input_size, input_dim), 0);

  ccv_nnc_tensor_t* b = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, batch_size, output_size, output_size, output_dim), 0);

  ccv_nnc_cmd_t cmd = CMD_CONVOLUTION_FORWARD(1, output_dim, kernel_size, kernel_size, input_dim);

  cmd.backend = CCV_NNC_BACKEND_CPU_REF;

  assert(cmd.backend >= 0);

  ccv_nnc_hint_t hint = ccv_nnc_hint_auto(cmd.info, a->info, b->info);

  assert(ccv_nnc_hint_verify(hint, cmd.info, a->info, b->info) == 0);

  ccv_nnc_tensor_t* w = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, output_dim, kernel_size, kernel_size, input_dim), 0);

  ccv_nnc_tensor_t* bias = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, output_dim), 0);

  dsfmt_t dsfmt;

  dsfmt_init_gen_rand(&dsfmt, 10);

  int i;

  for (i = 0; i < input_dim * kernel_size * kernel_size * output_dim; i++)

    w->data.f32[i] = (dsfmt_genrand_open_close(&dsfmt) - 0.5) / (input_dim * kernel_size * kernel_size);

  for (i = 0; i < input_size * input_size * input_dim * batch_size; i++)

    a->data.f32[i] = dsfmt_genrand_open_close(&dsfmt) - 0.5;

  for (i = 0; i < output_dim; i++)

    bias->data.f32[i] = (dsfmt_genrand_open_close(&dsfmt) - 0.5) * 0.1;

  const int input_count = batch_size * input_size * input_size * input_dim;

  const int weight_count = output_dim * kernel_size * kernel_size * input_dim;

  const int output_count = batch_size * output_size * output_size * output_dim;

  ccv_nnc_tensor_t* a16bf = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(16BF, batch_size, input_size, input_size, input_dim), 0);

  ccv_nnc_tensor_t* w16bf = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(16BF, output_dim, kernel_size, kernel_size, input_dim), 0);

  ccv_nnc_tensor_t* bias16bf = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(16BF, output_dim), 0);

  ccv_float_to_bfloat(a->data.f32, (uint16_t*)a16bf->data.f16, input_count);

  ccv_float_to_bfloat(w->data.f32, (uint16_t*)w16bf->data.f16, weight_count);

  ccv_float_to_bfloat(bias->data.f32, (uint16_t*)bias16bf->data.f16, output_dim);

  ccv_bfloat_to_float((uint16_t*)a16bf->data.f16, a->data.f32, input_count);

  ccv_bfloat_to_float((uint16_t*)w16bf->data.f16, w->data.f32, weight_count);

  ccv_bfloat_to_float((uint16_t*)bias16bf->data.f16, bias->data.f32, output_dim);

  ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(a, w, bias), TENSOR_LIST(b), 0);

  ccv_nnc_tensor_t* b16bf = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(16BF, batch_size, output_size, output_size, output_dim), 0);

  ccv_float_to_bfloat(b->data.f32, (uint16_t*)b16bf->data.f16, output_count);

  ccv_bfloat_to_float((uint16_t*)b16bf->data.f16, b->data.f32, output_count);

  ccv_nnc_tensor_t* ga = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 16BF, batch_size, input_size, input_size, input_dim), 0);

  ccv_nnc_tensor_t* gw = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 16BF, output_dim, kernel_size, kernel_size, input_dim), 0);

  ccv_nnc_tensor_t* gwo = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 16BF, output_dim, input_dim, kernel_size, kernel_size), 0);

  ccv_nnc_tensor_t* gbias = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 16BF, output_dim), 0);

  ccv_nnc_tensor_t* gc = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 16BF, batch_size, output_size, output_size, output_dim), 0);

  ccv_nnc_cmd_t move = CMD_DATA_TRANSFER_FORWARD();

  move.backend = CCV_NNC_BACKEND_MPS;

  assert(move.backend >= 0);

  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, TENSOR_LIST(a16bf, w16bf, bias16bf), TENSOR_LIST(ga, gw, gbias), 0);

  ccv_nnc_cmd_t transform = CMD_FORMAT_TRANSFORM_FORWARD();

  transform.backend = CCV_NNC_BACKEND_MPS;

  assert(transform.backend >= 0);

  ccv_nnc_stream_context_t* stream_context = ccv_nnc_stream_context_new(CCV_STREAM_CONTEXT_GPU);

  ccv_nnc_cmd_exec(transform, ccv_nnc_no_hint, 0, TENSOR_LIST(gw), TENSOR_LIST(gwo), stream_context);

  ccv_nnc_stream_context_wait(stream_context);

  ccv_nnc_tensor_free(gw);

  cmd.backend = CCV_NNC_BACKEND_MPS;

  assert(cmd.backend >= 0);

  cmd.algorithm = -1;

  cmd = ccv_nnc_cmd_autotune(cmd, 1 * 1024 * 1024 * 1024, hint, 0, TENSOR_LIST(ga, gwo, gbias), TENSOR_LIST(gc), stream_context);

  assert(CCV_NNC_EXEC_SUCCESS == ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(ga, gwo, gbias), TENSOR_LIST(gc), stream_context));

  ccv_nnc_stream_context_wait(stream_context);

  ccv_nnc_stream_context_free(stream_context);

  ccv_nnc_tensor_t* c16bf = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(16BF, batch_size, output_size, output_size, output_dim), 0);

  ccv_nnc_tensor_t* c = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, batch_size, output_size, output_size, output_dim), 0);

  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, TENSOR_LIST(gc), TENSOR_LIST(c16bf), 0);

  ccv_bfloat_to_float((uint16_t*)c16bf->data.f16, c->data.f32, output_count);

  REQUIRE_ARRAY_EQ_WITH_TOLERANCE(float, b->data.f32, c->data.f32, output_count, 5e-2, "bfloat output from mps should match CPU reference rounded to bfloat");

  ccv_nnc_tensor_free(c);

  ccv_nnc_tensor_free(c16bf);

  ccv_nnc_tensor_free(gc);

  ccv_nnc_tensor_free(gbias);

  ccv_nnc_tensor_free(gwo);

  ccv_nnc_tensor_free(ga);

  ccv_nnc_tensor_free(b16bf);

  ccv_nnc_tensor_free(bias16bf);

  ccv_nnc_tensor_free(w16bf);

  ccv_nnc_tensor_free(a16bf);

  ccv_nnc_tensor_free(bias);

  ccv_nnc_tensor_free(w);

  ccv_nnc_tensor_free(b);

  ccv_nnc_tensor_free(a);

}

TEST_CASE("mps forward convolution in bfloat precision with 1x1 kernel")

{

  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_CONVOLUTION_FORWARD, CCV_NNC_BACKEND_MPS));

  const int batch_size = 2;

  const int input_size = 17;

  const int output_size = 17;

  const int input_dim = 16;

  const int output_dim = 32;

  ccv_nnc_tensor_t* a = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, batch_size, input_size, input_size, input_dim), 0);

  ccv_nnc_tensor_t* b = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, batch_size, output_size, output_size, output_dim), 0);

  ccv_nnc_cmd_t cmd = CMD_CONVOLUTION_FORWARD(1, output_dim, 1, 1, input_dim);

  cmd.backend = CCV_NNC_BACKEND_CPU_REF;

  assert(cmd.backend >= 0);

  ccv_nnc_hint_t hint = ccv_nnc_hint_auto(cmd.info, a->info, b->info);

  assert(ccv_nnc_hint_verify(hint, cmd.info, a->info, b->info) == 0);

  ccv_nnc_tensor_t* w = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, output_dim, 1, 1, input_dim), 0);

  ccv_nnc_tensor_t* bias = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, output_dim), 0);

  dsfmt_t dsfmt;

  dsfmt_init_gen_rand(&dsfmt, 11);

  int i;

  for (i = 0; i < input_dim * output_dim; i++)

    w->data.f32[i] = (dsfmt_genrand_open_close(&dsfmt) - 0.5) / input_dim;

  for (i = 0; i < input_size * input_size * input_dim * batch_size; i++)

    a->data.f32[i] = dsfmt_genrand_open_close(&dsfmt) - 0.5;

  for (i = 0; i < output_dim; i++)

    bias->data.f32[i] = (dsfmt_genrand_open_close(&dsfmt) - 0.5) * 0.1;

  const int input_count = batch_size * input_size * input_size * input_dim;

  const int weight_count = output_dim * input_dim;

  const int output_count = batch_size * output_size * output_size * output_dim;

  ccv_nnc_tensor_t* a16bf = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(16BF, batch_size, input_size, input_size, input_dim), 0);

  ccv_nnc_tensor_t* w16bf = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(16BF, output_dim, 1, 1, input_dim), 0);

  ccv_nnc_tensor_t* bias16bf = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(16BF, output_dim), 0);

  ccv_float_to_bfloat(a->data.f32, (uint16_t*)a16bf->data.f16, input_count);

  ccv_float_to_bfloat(w->data.f32, (uint16_t*)w16bf->data.f16, weight_count);

  ccv_float_to_bfloat(bias->data.f32, (uint16_t*)bias16bf->data.f16, output_dim);

  ccv_bfloat_to_float((uint16_t*)a16bf->data.f16, a->data.f32, input_count);

  ccv_bfloat_to_float((uint16_t*)w16bf->data.f16, w->data.f32, weight_count);

  ccv_bfloat_to_float((uint16_t*)bias16bf->data.f16, bias->data.f32, output_dim);

  ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(a, w, bias), TENSOR_LIST(b), 0);

  ccv_nnc_tensor_t* b16bf = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(16BF, batch_size, output_size, output_size, output_dim), 0);

  ccv_float_to_bfloat(b->data.f32, (uint16_t*)b16bf->data.f16, output_count);

  ccv_bfloat_to_float((uint16_t*)b16bf->data.f16, b->data.f32, output_count);

  ccv_nnc_tensor_t* ga = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 16BF, batch_size, input_size, input_size, input_dim), 0);

  ccv_nnc_tensor_t* gw = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 16BF, output_dim, 1, 1, input_dim), 0);

  ccv_nnc_tensor_t* gwo = ccv_nnc_tensor_new(0, GPU_TENSOR_NCHW(000, 16BF, output_dim, input_dim, 1, 1), 0);

  ccv_nnc_tensor_t* gbias = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 16BF, output_dim), 0);

  ccv_nnc_tensor_t* gc = ccv_nnc_tensor_new(0, GPU_TENSOR_NHWC(000, 16BF, batch_size, output_size, output_size, output_dim), 0);

  ccv_nnc_cmd_t move = CMD_DATA_TRANSFER_FORWARD();

  move.backend = CCV_NNC_BACKEND_MPS;

  assert(move.backend >= 0);

  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, TENSOR_LIST(a16bf, w16bf, bias16bf), TENSOR_LIST(ga, gw, gbias), 0);

  ccv_nnc_cmd_t transform = CMD_FORMAT_TRANSFORM_FORWARD();

  transform.backend = CCV_NNC_BACKEND_MPS;

  assert(transform.backend >= 0);

  ccv_nnc_stream_context_t* stream_context = ccv_nnc_stream_context_new(CCV_STREAM_CONTEXT_GPU);

  ccv_nnc_cmd_exec(transform, ccv_nnc_no_hint, 0, TENSOR_LIST(gw), TENSOR_LIST(gwo), stream_context);

  ccv_nnc_stream_context_wait(stream_context);

  ccv_nnc_tensor_free(gw);

  cmd.backend = CCV_NNC_BACKEND_MPS;

  assert(cmd.backend >= 0);

  cmd.algorithm = -1;

  cmd = ccv_nnc_cmd_autotune(cmd, 1 * 1024 * 1024 * 1024, hint, 0, TENSOR_LIST(ga, gwo, gbias), TENSOR_LIST(gc), stream_context);

  assert(CCV_NNC_EXEC_SUCCESS == ccv_nnc_cmd_exec(cmd, hint, 0, TENSOR_LIST(ga, gwo, gbias), TENSOR_LIST(gc), stream_context));

  ccv_nnc_stream_context_wait(stream_context);

  ccv_nnc_stream_context_free(stream_context);

  ccv_nnc_tensor_t* c16bf = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(16BF, batch_size, output_size, output_size, output_dim), 0);

  ccv_nnc_tensor_t* c = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, batch_size, output_size, output_size, output_dim), 0);

  ccv_nnc_cmd_exec(move, ccv_nnc_no_hint, 0, TENSOR_LIST(gc), TENSOR_LIST(c16bf), 0);

  ccv_bfloat_to_float((uint16_t*)c16bf->data.f16, c->data.f32, output_count);

  REQUIRE_ARRAY_EQ_WITH_TOLERANCE(float, b->data.f32, c->data.f32, output_count, 5e-2, "bfloat output from mps 1x1 convolution should match CPU reference rounded to bfloat");

  ccv_nnc_tensor_free(c);

  ccv_nnc_tensor_free(c16bf);

  ccv_nnc_tensor_free(gc);

  ccv_nnc_tensor_free(gbias);

  ccv_nnc_tensor_free(gwo);

  ccv_nnc_tensor_free(ga);

  ccv_nnc_tensor_free(b16bf);

  ccv_nnc_tensor_free(bias16bf);

  ccv_nnc_tensor_free(w16bf);

  ccv_nnc_tensor_free(a16bf);

  ccv_nnc_tensor_free(bias);

  ccv_nnc_tensor_free(w);

  ccv_nnc_tensor_free(b);

  ccv_nnc_tensor_free(a);

}

TEST_CASE("mps forward convolution with dilation 2, 3")

{

  GUARD_ELSE_RETURN(ccv_nnc_cmd_ok(CCV_NNC_CONVOLUTION_FORWARD, CCV_NNC_BACKEND_MPS));

  ccv_nnc_tensor_t* a = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, BATCH_SIZE, INPUT_SIZE, INPUT_SIZE, INPUT_DIM), 0);

  ccv_nnc_tensor_t* b = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, BATCH_SIZE, OUTPUT_SIZE, OUTPUT_SIZE, OUTPUT_DIM), 0);

  ccv_nnc_cmd_t cmd = CMD_CONVOLUTION_FORWARD(1, OUTPUT_DIM, KERNEL_SIZE, KERNEL_SIZE, INPUT_DIM);

  cmd.info.convolution.dilation[0] = 2;

  cmd.info.convolution.dilation[1] = 3;

  cmd.backend = CCV_NNC_BACKEND_CPU_REF;

  assert(cmd.backend >= 0);

  ccv_nnc_cmd_param_t modified_cmd = cmd.info;

  modified_cmd.size.dim[0] = (cmd.info.size.dim[0] - 1) * ccv_max(cmd.info.convolution.dilation[0], 1) + 1;

  modified_cmd.size.dim[1] = (cmd.info.size.dim[1] - 1) * ccv_max(cmd.info.convolution.dilation[1], 1) + 1;

  ccv_nnc_hint_t hint = ccv_nnc_hint_auto(modified_cmd, a->info, b->info);

  assert(ccv_nnc_hint_verify(hint, modified_cmd, a->info, b->info) == 0);

  ccv_nnc_tensor_t* w = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, OUTPUT_DIM, KERNEL_SIZE, KERNEL_SIZE, INPUT_DIM), 0);

  ccv_nnc_tensor_t* bias = ccv_nnc_tensor_new(0, CPU_TENSOR_NHWC(32F, OUTPUT_DIM), 0);

  // configure the inlets.

  dsfmt_t dsfmt;

  dsfmt_init_gen_rand(&dsfmt, 0);

  int i;

  for (i = 0; i < INPUT_DIM * KERNEL_SIZE * KERNEL_SIZE * OUTPUT_DIM; i++)

    w->data.f32[i] = dsfmt_genrand_open_close(&dsfmt) / (INPUT_DIM * KERNEL_SIZE * KERNEL_SIZE);

  for (i = 0; i < INPUT_SIZE * INPUT_SIZE * INPUT_DIM * ccv_max(1, BATCH_SIZE); i++)